627 lines
27 KiB
Plaintext
627 lines
27 KiB
Plaintext
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(kicad_pcb (version 4) (host pcbnew "(2015-12-10 BZR 6367, Git c5e9bda)-product")
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(general
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(links 48)
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(no_connects 48)
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(area 120.44 83.55 175.833397 115.503201)
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(thickness 1.6)
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(drawings 0)
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(tracks 0)
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(zones 0)
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(modules 14)
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(nets 31)
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)
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(page A4)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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(32 B.Adhes user)
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(33 F.Adhes user)
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(34 B.Paste user)
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(35 F.Paste user)
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(36 B.SilkS user)
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(37 F.SilkS user)
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(38 B.Mask user)
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(39 F.Mask user)
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(40 Dwgs.User user)
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(41 Cmts.User user)
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(42 Eco1.User user)
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(43 Eco2.User user)
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(44 Edge.Cuts user)
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(45 Margin user)
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(46 B.CrtYd user)
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(47 F.CrtYd user)
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(48 B.Fab user)
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(49 F.Fab user)
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)
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(setup
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(last_trace_width 0.25)
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(trace_clearance 0.2)
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(zone_clearance 0.508)
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(zone_45_only no)
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(trace_min 0.2)
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(segment_width 0.2)
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(edge_width 0.15)
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(via_size 0.6)
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(via_drill 0.4)
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(via_min_size 0.4)
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(via_min_drill 0.3)
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(uvia_size 0.3)
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(uvia_drill 0.1)
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(uvias_allowed no)
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(uvia_min_size 0.2)
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(uvia_min_drill 0.1)
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(pcb_text_width 0.3)
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(pcb_text_size 1.5 1.5)
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(mod_edge_width 0.15)
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(mod_text_size 1 1)
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(mod_text_width 0.15)
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(pad_size 1.524 1.524)
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(pad_drill 0.762)
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(pad_to_mask_clearance 0.2)
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(aux_axis_origin 0 0)
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(visible_elements FFFFFF7F)
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(pcbplotparams
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(layerselection 0x00030_ffffffff)
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(usegerberextensions false)
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(excludeedgelayer true)
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(linewidth 0.100000)
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(plotframeref false)
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(viasonmask false)
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(mode 1)
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(useauxorigin false)
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(hpglpennumber 1)
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(hpglpenspeed 20)
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(hpglpendiameter 15)
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(hpglpenoverlay 2)
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(psnegative false)
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(psa4output false)
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(plotreference true)
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(plotvalue true)
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(plotinvisibletext false)
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(padsonsilk false)
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(subtractmaskfromsilk false)
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(outputformat 1)
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(mirror false)
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(drillshape 1)
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(scaleselection 1)
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(outputdirectory ""))
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)
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(net 0 "")
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(net 1 +5V)
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(net 2 GND)
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(net 3 "Net-(IC1-Pad2)")
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(net 4 "Net-(IC1-Pad3)")
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(net 5 "Net-(IC1-Pad4)")
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(net 6 "Net-(IC1-Pad5)")
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(net 7 "Net-(IC1-Pad6)")
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(net 8 "Net-(IC1-Pad10)")
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(net 9 "Net-(IC1-Pad11)")
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(net 10 "Net-(IC1-Pad12)")
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(net 11 "Net-(IC1-Pad13)")
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(net 12 "Net-(IC1-Pad23)")
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(net 13 "Net-(IC1-Pad24)")
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(net 14 "Net-(IC1-Pad25)")
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(net 15 "Net-(IC1-Pad26)")
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(net 16 "Net-(IC1-Pad27)")
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(net 17 "Net-(IC1-Pad28)")
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(net 18 "Net-(RV1-Pad2)")
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(net 19 "Net-(S1-Pad7)")
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(net 20 "Net-(S1-Pad8)")
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(net 21 "Net-(S1-Pad9)")
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(net 22 "Net-(S1-Pad10)")
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(net 23 /D7)
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(net 24 /RS)
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(net 25 "Net-(CON1-Pad5)")
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(net 26 /RW)
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(net 27 /E)
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(net 28 /D4)
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(net 29 /D5)
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(net 30 /D6)
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(net_class Default "This is the default net class."
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(clearance 0.2)
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(trace_width 0.25)
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(via_dia 0.6)
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(via_drill 0.4)
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(uvia_dia 0.3)
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(uvia_drill 0.1)
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(add_net +5V)
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(add_net /D4)
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(add_net /D5)
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(add_net /D6)
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(add_net /D7)
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(add_net /E)
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(add_net /RS)
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(add_net /RW)
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(add_net GND)
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(add_net "Net-(CON1-Pad5)")
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(add_net "Net-(IC1-Pad10)")
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(add_net "Net-(IC1-Pad11)")
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(add_net "Net-(IC1-Pad12)")
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(add_net "Net-(IC1-Pad13)")
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(add_net "Net-(IC1-Pad2)")
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(add_net "Net-(IC1-Pad23)")
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(add_net "Net-(IC1-Pad24)")
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(add_net "Net-(IC1-Pad25)")
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(add_net "Net-(IC1-Pad26)")
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(add_net "Net-(IC1-Pad27)")
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(add_net "Net-(IC1-Pad28)")
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(add_net "Net-(IC1-Pad3)")
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(add_net "Net-(IC1-Pad4)")
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(add_net "Net-(IC1-Pad5)")
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(add_net "Net-(IC1-Pad6)")
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(add_net "Net-(RV1-Pad2)")
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(add_net "Net-(S1-Pad10)")
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(add_net "Net-(S1-Pad7)")
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(add_net "Net-(S1-Pad8)")
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(add_net "Net-(S1-Pad9)")
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)
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(module capacitors:cnp_7x2mm (layer F.Cu) (tedit 4B90D4E6) (tstamp 56984BA6)
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(at 116.9 71.95)
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(descr "Capacitor non pol, 7x2,5mm")
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(path /56947309)
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(fp_text reference C1 (at 0 -3.048) (layer F.SilkS)
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(effects (font (thickness 0.3048)))
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)
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(fp_text value C (at 0 2.794) (layer F.SilkS)
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(effects (font (thickness 0.3048)))
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)
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(fp_line (start -3.81 -1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.254))
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(fp_line (start 3.81 -1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.254))
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(fp_line (start 3.81 1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.254))
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(fp_line (start -3.81 1.27) (end -3.81 -1.27) (layer F.SilkS) (width 0.254))
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(pad 1 thru_hole circle (at -2.54 0) (size 1.99898 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
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(net 1 +5V))
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(pad 2 thru_hole circle (at 2.54 0) (size 1.99898 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
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(net 2 GND))
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(model discret/capacitor/cnp_7x2mm.wrl
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(at (xyz 0 0 0))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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)
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)
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(module capacitors:cnp_7x2mm (layer F.Cu) (tedit 4B90D4E6) (tstamp 56984BAC)
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(at 118.22 51.11 180)
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(descr "Capacitor non pol, 7x2,5mm")
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(path /569474CE)
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(fp_text reference C2 (at 0 -3.048 180) (layer F.SilkS)
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(effects (font (thickness 0.3048)))
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)
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(fp_text value C (at 0 2.794 180) (layer F.SilkS)
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(effects (font (thickness 0.3048)))
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)
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(fp_line (start -3.81 -1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.254))
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(fp_line (start 3.81 -1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.254))
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(fp_line (start 3.81 1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.254))
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(fp_line (start -3.81 1.27) (end -3.81 -1.27) (layer F.SilkS) (width 0.254))
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(pad 1 thru_hole circle (at -2.54 0 180) (size 1.99898 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
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(net 1 +5V))
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(pad 2 thru_hole circle (at 2.54 0 180) (size 1.99898 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
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(net 2 GND))
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(model discret/capacitor/cnp_7x2mm.wrl
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(at (xyz 0 0 0))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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)
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)
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(module capacitors:cnp_7x2mm (layer F.Cu) (tedit 4B90D4E6) (tstamp 56984BB2)
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(at 115.33 54.28 180)
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(descr "Capacitor non pol, 7x2,5mm")
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(path /5694756E)
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(fp_text reference C3 (at 0 -3.048 180) (layer F.SilkS)
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(effects (font (thickness 0.3048)))
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)
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(fp_text value C (at 0 2.794 180) (layer F.SilkS)
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(effects (font (thickness 0.3048)))
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)
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(fp_line (start -3.81 -1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.254))
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(fp_line (start 3.81 -1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.254))
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||
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(fp_line (start 3.81 1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.254))
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(fp_line (start -3.81 1.27) (end -3.81 -1.27) (layer F.SilkS) (width 0.254))
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(pad 1 thru_hole circle (at -2.54 0 180) (size 1.99898 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
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(net 1 +5V))
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||
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(pad 2 thru_hole circle (at 2.54 0 180) (size 1.99898 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
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(net 2 GND))
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(model discret/capacitor/cnp_7x2mm.wrl
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(at (xyz 0 0 0))
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(scale (xyz 1 1 1))
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(rotate (xyz 0 0 0))
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)
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)
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(module capacitors:cnp_7x2mm (layer F.Cu) (tedit 4B90D4E6) (tstamp 56984BB8)
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(at 104.3 90.39)
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(descr "Capacitor non pol, 7x2,5mm")
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||
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(path /569771FD)
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||
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(fp_text reference C4 (at 0 -3.048) (layer F.SilkS)
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||
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(effects (font (thickness 0.3048)))
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||
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)
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||
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(fp_text value C (at 0 2.794) (layer F.SilkS)
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||
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(effects (font (thickness 0.3048)))
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||
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)
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||
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(fp_line (start -3.81 -1.27) (end 3.81 -1.27) (layer F.SilkS) (width 0.254))
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||
|
|
(fp_line (start 3.81 -1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.254))
|
||
|
|
(fp_line (start 3.81 1.27) (end -3.81 1.27) (layer F.SilkS) (width 0.254))
|
||
|
|
(fp_line (start -3.81 1.27) (end -3.81 -1.27) (layer F.SilkS) (width 0.254))
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||
|
|
(pad 1 thru_hole circle (at -2.54 0) (size 1.99898 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
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||
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|
(net 2 GND))
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||
|
|
(pad 2 thru_hole circle (at 2.54 0) (size 1.99898 1.99898) (drill 0.8001) (layers *.Cu *.Mask F.SilkS)
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||
|
|
(net 1 +5V))
|
||
|
|
(model discret/capacitor/cnp_7x2mm.wrl
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||
|
|
(at (xyz 0 0 0))
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||
|
|
(scale (xyz 1 1 1))
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||
|
|
(rotate (xyz 0 0 0))
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||
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)
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||
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)
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||
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||
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|
(module dip_sockets:DIP-28__300_ELL (layer F.Cu) (tedit 200000) (tstamp 56984BD8)
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||
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(at 116.59 61.22)
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||
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(descr "28 pins DIL package, elliptical pads, width 300mil")
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||
|
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(tags DIL)
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||
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|
(path /569471D6)
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||
|
|
(fp_text reference IC1 (at -11.43 0) (layer F.SilkS)
|
||
|
|
(effects (font (size 1.524 1.143) (thickness 0.3048)))
|
||
|
|
)
|
||
|
|
(fp_text value ATMEGA328-P (at 6.985 0) (layer F.SilkS)
|
||
|
|
(effects (font (size 1.524 1.143) (thickness 0.3048)))
|
||
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)
|
||
|
|
(fp_line (start -19.05 -2.54) (end 19.05 -2.54) (layer F.SilkS) (width 0.381))
|
||
|
|
(fp_line (start 19.05 -2.54) (end 19.05 2.54) (layer F.SilkS) (width 0.381))
|
||
|
|
(fp_line (start 19.05 2.54) (end -19.05 2.54) (layer F.SilkS) (width 0.381))
|
||
|
|
(fp_line (start -19.05 2.54) (end -19.05 -2.54) (layer F.SilkS) (width 0.381))
|
||
|
|
(fp_line (start -19.05 -1.27) (end -17.78 -1.27) (layer F.SilkS) (width 0.381))
|
||
|
|
(fp_line (start -17.78 -1.27) (end -17.78 1.27) (layer F.SilkS) (width 0.381))
|
||
|
|
(fp_line (start -17.78 1.27) (end -19.05 1.27) (layer F.SilkS) (width 0.381))
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||
|
|
(pad 2 thru_hole oval (at -13.97 3.81) (size 1.5748 2.286) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
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||
|
|
(net 3 "Net-(IC1-Pad2)"))
|
||
|
|
(pad 3 thru_hole oval (at -11.43 3.81) (size 1.5748 2.286) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
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||
|
|
(net 4 "Net-(IC1-Pad3)"))
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||
|
|
(pad 4 thru_hole oval (at -8.89 3.81) (size 1.5748 2.286) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
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||
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(net 5 "Net-(IC1-Pad4)"))
|
||
|
|
(pad 5 thru_hole oval (at -6.35 3.81) (size 1.5748 2.286) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
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||
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(net 6 "Net-(IC1-Pad5)"))
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||
|
|
(pad 6 thru_hole oval (at -3.81 3.81) (size 1.5748 2.286) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
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||
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(net 7 "Net-(IC1-Pad6)"))
|
||
|
|
(pad 7 thru_hole oval (at -1.27 3.81) (size 1.5748 2.286) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
|
||
|
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(net 1 +5V))
|
||
|
|
(pad 8 thru_hole oval (at 1.27 3.81) (size 1.5748 2.286) (drill 0.8128) (layers *.Cu *.Mask F.SilkS)
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||
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|
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(at 79.18 65.55 180)
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|
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(descr "Resistance 5 pas")
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(tags R)
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)
|
||
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|
||
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(module discret:R5 (layer B.Cu) (tedit 200000) (tstamp 56984BE4)
|
||
|
|
(at 172.62 63.21)
|
||
|
|
(descr "Resistance 5 pas")
|
||
|
|
(tags R)
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(path /5697629E)
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||
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|
||
|
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|
||
|
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(scale (xyz 0.5 0.5 0.5))
|
||
|
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|
||
|
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)
|
||
|
|
)
|
||
|
|
|
||
|
|
(module Potentiometres:POACAH (layer F.Cu) (tedit 49337FE6) (tstamp 56984BEB)
|
||
|
|
(at 138.43 33.79 90)
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||
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||
|
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|
||
|
|
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|
||
|
|
|
||
|
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|
||
|
|
(at 117.62 43.16)
|
||
|
|
(descr "16 pins connector")
|
||
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|
||
|
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|
||
|
|
|
||
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|
||
|
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||
|
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|
||
|
|
)
|
||
|
|
|
||
|
|
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|
||
|
|
(at 172.4 63.31)
|
||
|
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(path /56976205)
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