Generalized clock entity

Added generic "freq" to clock entity to allow choice of the frequency of
clock that will be generated. Remember, this entity is for simulation
purposes only!

Signed-off-by: Collin J. Doering <collin.doering@rekahsoft.ca>

src/clock.vhdl

@@ -16,20 +16,22 @@
 -- File: clock.vhdl
 -- Author: Collin J. Doering <collin.doering@rekahsoft.ca>
 -- Date: May 22, 2015
+-- Description: A clock entity for use for simulation only!
 
 library IEEE;
 use IEEE.std_logic_1164.all;
 
 entity clock is
+  generic (freq : real := 1000000000.0);
   port (finish : in  std_logic;
         cout   : out std_logic);
 end clock;
 
 architecture clock_arch of clock is
   signal clk: std_logic := '0';
+  constant period : time := 1 sec / freq;
+  constant half_period : time := period / 2;
 begin
-  clk <= '0' when finish = '1' else
-         '1' after 0.5 ns when clk = '0' else
-         '0' after 0.5 ns when clk = '1';
+  clk <= not clk after half_period when finish /= '1' else '0';
   cout <= clk;
 end clock_arch;

src/clock_tb.vhdl

@@ -27,6 +27,7 @@ end clock_tb;
 architecture clock_tb_arch of clock_tb is
    --  Declaration of the component that will be instantiated.
    component clock
+     generic (freq : real := 1000000000.0);
      port (finish : in  std_logic;
            cout   : out std_logic);
    end component;
@@ -35,10 +36,12 @@ architecture clock_tb_arch of clock_tb is
    for clock_0: clock use entity work.clock;
 
    -- Signals
-   signal finish, cout : std_logic;
+   signal finish, finish_1, cout, cout_1 : std_logic;
 begin
   --  Component instantiation.
    clock_0: clock port map (finish, cout);
+   clock_1: clock generic map (freq => 1000000.0)
+                  port map (finish_1, cout_1);
 
    --  This process does the real job.
    process
@@ -95,7 +98,10 @@ begin
          ('0', '1'));
          
    begin
-      --  Check each pattern.
+      -- Set 1 MHz clock 'on'
+      finish_1 <= '0';
+
+      --  Check each pattern. Tests whether the finish bit works correctly.
       for i in patterns'range loop
          --  Set the inputs.
          finish <= patterns(i).finish;
@@ -105,8 +111,14 @@ begin
            report "bad clock" severity error;
          wait for 0.4 ns;
       end loop;
-      -- End the clock
+
+      -- Wait for an additional 1 ms
+      wait for 1 ms;
+
+      -- End the clocks
       finish <= '1';
+      finish_1 <= '1';
+
       assert false report "end of test" severity note;
       --  Wait forever; this will finish the simulation.
       wait;

src/wave/gtkw/clock.gtkw

@@ -0,0 +1,34 @@
+[*]
+[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
+[*] Mon Jun  1 01:40:12 2015
+[*]
+[dumpfile] "/home/collin/.code/my-projects/public/hack/src/wave/vcd/clock.vcd"
+[dumpfile_mtime] "Fri May 29 04:19:57 2015"
+[dumpfile_size] 45797442
+[savefile] "/home/collin/.code/my-projects/public/hack/src/wave/gtkw/clock.gtkw"
+[timestart] 0
+[size] 1916 1196
+[pos] -1 -1
+*-31.034330 4170000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] clock_0.
+[sst_width] 250
+[signals_width] 187
+[sst_expanded] 1
+[sst_vpaned_height] 349
+@800200
+-clock_0 : 1 GHz
+@28
+clock_0.cout
+clock_0.finish
+@1000200
+-clock_0 : 1 GHz
+@800200
+-clock_1 : 1 MHz
+@28
+clock_1.cout
+@29
+clock_1.finish
+@1000200
+-clock_1 : 1 MHz
+[pattern_trace] 1
+[pattern_trace] 0