Added generic "freq" to clock entity to allow choice of the frequency of
clock that will be generated. Remember, this entity is for simulation
purposes only!
Signed-off-by: Collin J. Doering <collin.doering@rekahsoft.ca>
Contains vhdl code and test benches for the following chips:
- adder
- add16
- alu
- dff
- dbit
- dregister
- dmux
- dmux4way
- dmux8way
- mux
- mux16
- mux4way16
- mux8way16
- pc
- ram8
- ram64
- ram512
- ram4k
- ram16k
For simulation of sequential chips, a clock must be used; this is
implemented as 'src/clock.vhdl' with accompanying test bench
'src/clock_tb.vhdl'.
'src/wave/gktw' contains gtkwave save files for viewing the output of
the various test benches.
The 'schematics' directory contains schematics of the various
chips (incomplete).
Things not yet completed:
- weird issue with 'src/pc_tb.vhdl'; that is, the test data from the
"nand to tetris" course doesn't fit the simulation but the simulation
appears to be correct (by inspection).
- cpu chip
- build system (currently things can built by hand using ghdl as
follows)
To build the various chips and their respective test benches, use ghdl
like so:
$ cd src
$ ghdl -i --workdir=work *.vhdl
$ ghdl -m --workdir=work <chip_name>_tb
$ ghdl -r <chip_name>_tb --vcd=wave/vcd/<chip_name>.vcd
You can then view the wave output file in
'src/wave/vcd/<chip_name>.vcd'.
Collin J. Doering