Commit Graph

4 Commits

Author SHA1 Message Date
Collin J. Doering 0c737a29d9 Preliminary implementation of Hack computer simulation
Added two additional VHDL units 'src/ROM.vhdl' and
"src/computer_tb.vhdl", both of which are only meant for simulation
purposes. The ROM unit loads a text file specified by the generic property
"program_file" and acts as a 32K ROM addressed by its line
number (starting with zero). The computer_tb unit puts everything
together (cpu, ROM, and ram16k) and allows the user to pass a program
file via a generic property. This program file must contain less than
65535 lines containing 16 zeros or ones (eg. Something generated by the
assembler given for the Nand to Tetris course).

The directory "src/asm" was added containing a couple test programs in
both hack assembly and in hack machine language. Additionally, various
gtkwave save files (in 'src/wave/gtkw') were added for use with each
hack program given, as well as two template gtkwave save files for use
with new programs.

See the README.md file for more details on running simulations with
computer_tb, as well as various other details.

TODO: implement memory maps for screen and keyboard and handle VGA
      output

Signed-off-by: Collin J. Doering <collin.doering@rekahsoft.ca>
2015-06-05 19:14:14 -04:00
Collin J. Doering 90c8cc2ea8 Fix gitignore files
Ignore everything but vhdl source files in src, instead of at top level.

Signed-off-by: Collin J. Doering <collin.doering@rekahsoft.ca>
2015-05-21 19:11:38 -04:00
Collin J. Doering 8415eb51c6 Minor modification to .gitignore
Avoid having executables show up in git status.
2015-05-21 18:33:27 -04:00
Collin J. Doering 6ab2badb26 Initial commit
Contains vhdl code and test benches for the following chips:

- adder
- add16
- alu
- dff
- dbit
- dregister
- dmux
- dmux4way
- dmux8way
- mux
- mux16
- mux4way16
- mux8way16
- pc
- ram8
- ram64
- ram512
- ram4k
- ram16k

For simulation of sequential chips, a clock must be used; this is
implemented as 'src/clock.vhdl' with accompanying test bench
'src/clock_tb.vhdl'.

'src/wave/gktw' contains gtkwave save files for viewing the output of
the various test benches.

The 'schematics' directory contains schematics of the various
chips (incomplete).

Things not yet completed:
- weird issue with 'src/pc_tb.vhdl'; that is, the test data from the
"nand to tetris" course doesn't fit the simulation but the simulation
appears to be correct (by inspection).
- cpu chip
- build system (currently things can built by hand using ghdl as
follows)

To build the various chips and their respective test benches, use ghdl
like so:
$ cd src
$ ghdl -i --workdir=work *.vhdl
$ ghdl -m --workdir=work <chip_name>_tb
$ ghdl -r <chip_name>_tb --vcd=wave/vcd/<chip_name>.vcd

You can then view the wave output file in
'src/wave/vcd/<chip_name>.vcd'.
2015-05-21 15:12:01 -04:00