127 lines
3.4 KiB
VHDL
127 lines
3.4 KiB
VHDL
-- (C) Copyright Collin J. Doering 2015
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- File: clock_tb.vhdl
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-- Author: Collin J. Doering <collin.doering@rekahsoft.ca>
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-- Date: May 22, 2015
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library IEEE;
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use IEEE.std_logic_1164.all;
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-- A testbench has no ports.
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entity clock_tb is
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end clock_tb;
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architecture clock_tb_arch of clock_tb is
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-- Declaration of the component that will be instantiated.
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component clock
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generic (freq : real := 1000000000.0);
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port (finish : in std_logic;
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cout : out std_logic);
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end component;
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-- Specifies which entity is bound with the component.
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for clock_0: clock use entity work.clock;
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-- Signals
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signal finish, finish_1, cout, cout_1 : std_logic;
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begin
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-- Component instantiation.
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clock_0: clock port map (finish, cout);
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clock_1: clock generic map (freq => 1000000.0)
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port map (finish_1, cout_1);
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-- This process does the real job.
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process
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type pattern_type is record
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-- The inputs of the clock.
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finish : std_logic;
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-- The output of the clock.
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cout : std_logic;
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end record;
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-- The patterns to apply.
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type pattern_array is array (natural range <>) of pattern_type;
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constant patterns : pattern_array :=
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(('0', '0'),
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('0', '1'),
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('0', '0'),
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('0', '1'),
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('0', '0'),
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('0', '1'),
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('0', '0'),
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('0', '1'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('0', '0'),
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('0', '1'),
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('0', '0'),
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('0', '1'),
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('0', '0'),
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('0', '1'),
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('0', '0'),
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('0', '1'),
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('0', '0'),
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('0', '1'),
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('0', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('1', '0'),
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('0', '0'),
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('0', '1'),
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('0', '0'),
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('0', '1'));
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begin
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-- Set 1 MHz clock 'on'
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finish_1 <= '0';
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-- Check each pattern. Tests whether the finish bit works correctly.
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for i in patterns'range loop
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-- Set the inputs.
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finish <= patterns(i).finish;
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wait for 0.1 ns;
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-- Check the outputs.
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assert cout = patterns(i).cout
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report "bad clock" severity error;
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wait for 0.4 ns;
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end loop;
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-- Wait for an additional 1 ms
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wait for 1 ms;
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-- End the clocks
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finish <= '1';
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finish_1 <= '1';
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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end process;
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end clock_tb_arch;
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