79 lines
2.6 KiB
VHDL
79 lines
2.6 KiB
VHDL
-- (C) Copyright Collin J. Doering 2015
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- File: computer_tb.vhdl
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-- Author: Collin J. Doering <collin.doering@rekahsoft.ca>
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-- Date: May 22, 2015
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library IEEE;
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use IEEE.std_logic_1164.all;
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use std.textio.all;
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entity computer_tb is
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generic (program_file : string := "asm/Fib.hack");
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end computer_tb;
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architecture computer_tb_arch of computer_tb is
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component clock
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generic (freq : real := 1000000000.0);
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port (finish : in std_logic;
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cout : out std_logic);
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end component;
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component ROM
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generic (program_file : string := program_file);
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port (address : in std_logic_vector(14 downto 0);
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clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end component;
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component ram16k
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port (d : in std_logic_vector(15 downto 0);
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load : in std_logic;
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address : in std_logic_vector(14 downto 0);
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clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end component;
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component cpu
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port (inM, instruction : in std_logic_vector(15 downto 0);
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reset, clk : in std_logic;
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outM : out std_logic_vector(15 downto 0);
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writeM : out std_logic;
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addressM, pcOut : out std_logic_vector(14 downto 0));
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end component;
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signal clk_fin, clk, reset, writeM : std_logic;
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signal ramIn, ramOut, romOut : std_logic_vector(15 downto 0);
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signal addressM, pcOut : std_logic_vector(14 downto 0);
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begin
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reset <= '0';
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clk_fin <= '0';
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OSC_CLK: clock port map (clk_fin, clk);
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INSR_ROM: ROM port map (pcOut, clk, romOut);
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MEMORY: ram16k port map (ramIn, writeM, addressM, clk, ramOut);
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THE_CPU: cpu port map (ramOut, romOut, reset, clk, ramIn, writeM, addressM, pcOut);
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process
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begin
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loop
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wait for 1 ns;
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assert false report "1 ns passed" severity note;
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end loop;
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end process;
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end computer_tb_arch;
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