39 lines
1.3 KiB
VHDL
39 lines
1.3 KiB
VHDL
-- (C) Copyright Collin J. Doering 2015
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- File: dregister.vhdl
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-- Author: Collin J. Doering <collin.doering@rekahsoft.ca>
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-- Date: May 22, 2015
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity dregister is
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port (d : in std_logic_vector(15 downto 0);
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load, clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end dregister;
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architecture dregister_arch of dregister is
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component dbit
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port (d, load, clk : in std_logic;
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cout : out std_logic);
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end component;
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begin
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reg: for i in 0 to 15 generate
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dbit_i: dbit port map (d(i), load, clk, cout(i));
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end generate;
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end dregister_arch;
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