83 lines
3.0 KiB
VHDL
83 lines
3.0 KiB
VHDL
-- (C) Copyright Collin J. Doering 2015
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- File: mux16_tb.vhdl
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-- Author: Collin J. Doering <collin.doering@rekahsoft.ca>
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-- Date: May 22, 2015
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library IEEE;
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use IEEE.std_logic_1164.all;
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-- A testbench has no ports.
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entity mux16_tb is
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end mux16_tb;
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architecture mux16_tb_arch of mux16_tb is
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-- Declaration of the component that will be instantiated.
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component mux16
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port (a, b : in std_logic_vector(15 downto 0);
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sel : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end component;
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-- Specifies which entity is bound with the component.
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for mux16_0: mux16 use entity work.mux16;
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-- Signals
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signal a, b, cout : std_logic_vector(15 downto 0);
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signal sel : std_logic;
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begin
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-- Component instantiation.
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mux16_0: mux16 port map (a => a, b => b, sel => sel, cout => cout);
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-- This process does the real job.
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process
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type pattern_type is record
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-- The inputs of the mux16.
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a, b : std_logic_vector(15 downto 0);
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sel : std_logic;
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-- The expected outputs of the mux16.
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cout : std_logic_vector(15 downto 0);
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end record;
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-- The patterns to apply.
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type pattern_array is array (natural range <>) of pattern_type;
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constant patterns : pattern_array :=
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(("0000000000000000", "0000000000000001", '0', "0000000000000000"),
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("0000000000000001", "0000000000000000", '1', "0000000000000000"),
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("0000000000000000", "1111111111111111", '0', "0000000000000000"),
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("0000000000000000", "1111111111111111", '1', "1111111111111111"),
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("1111111111111111", "0000000000000000", '0', "1111111111111111"),
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("1111111111111111", "0000000000000000", '1', "0000000000000000"),
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("1111111111111111", "1111111111111110", '0', "1111111111111111"),
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("1111111111111110", "1111111111111111", '1', "1111111111111111"));
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begin
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-- Check each pattern.
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for i in patterns'range loop
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-- Set the inputs.
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a <= patterns(i).a;
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b <= patterns(i).b;
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sel <= patterns(i).sel;
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-- Wait for the results.
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wait for 1 ns;
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-- Check the outputs.
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assert cout = patterns(i).cout
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report "bad mux16 output" severity error;
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end loop;
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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end process;
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end mux16_tb_arch;
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