142 lines
6.1 KiB
VHDL
142 lines
6.1 KiB
VHDL
-- (C) Copyright Collin J. Doering 2015
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- File: pc_tb.vhdl
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-- Author: Collin J. Doering <collin.doering@rekahsoft.ca>
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-- Date: May 22, 2015
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library IEEE;
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use IEEE.std_logic_1164.all;
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-- A testbench has no ports.
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entity pc_tb is
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end pc_tb;
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architecture pc_tb_arch of pc_tb is
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-- Declaration of the component that will be instantiated.
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component pc
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port (d : in std_logic_vector(15 downto 0);
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load, inc, reset, clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end component;
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-- Declaration of the clock
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component Clock
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port (finish : in std_logic;
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cout : out std_logic);
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end component;
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-- Specifies which entity is bound with the component.
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for pc_0: pc use entity work.pc;
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-- Signals
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signal d, cout : std_logic_vector(15 downto 0);
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signal load, inc, reset, finish, clk : std_logic;
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begin
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-- Component instantiation.
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OSC_CLK: Clock port map (finish, clk);
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pc_0: pc port map (d, load, inc, reset, clk, cout);
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-- This process does the real job.
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process
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type pattern_type is record
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-- The inputs of the pc.
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d : std_logic_vector(15 downto 0);
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reset, load, inc : std_logic;
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-- The output of the pc.
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cout : std_logic_vector(15 downto 0);
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end record;
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-- The patterns to apply.
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type pattern_array is array (natural range <>) of pattern_type;
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constant patterns : pattern_array :=
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(("0000000000000000", '0', '0', '0', "0000000000000000"), -- 0
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("0000000000000000", '0', '0', '0', "0000000000000000"), -- 1
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("0000000000000000", '0', '0', '1', "0000000000000000"), -- 2
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("0000000000000000", '0', '0', '1', "0000000000000001"), -- 3
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("0111110101111011", '0', '0', '1', "0000000000000010"), -- 4 (revised)
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("0111110101111011", '0', '0', '1', "0000000000000011"), -- 5 (revised)
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("0111110101111011", '0', '1', '1', "0000000000000100"), -- 6 (revised)
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-- ("0111110101111011", '0', '0', '1', "0000000000000001"), -- 4 (here)
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-- ("0111110101111011", '0', '0', '1', "0000000000000010"), -- 5 (here)
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-- ("0111110101111011", '0', '1', '1', "0000000000000010"), -- 6 (here)
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("0111110101111011", '0', '1', '1', "0111110101111011"), -- 7
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("0111110101111011", '0', '0', '1', "0111110101111011"), -- 8
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("0111110101111011", '0', '0', '1', "0111110101111100"), -- 9 (revised)
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("0111110101111011", '0', '0', '1', "0111110101111101"), -- 10 (revised)
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("0111110101111011", '0', '0', '1', "0111110101111110"), -- 11 (revised)
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("0011000000111001", '0', '1', '0', "0111110101111111"), -- 12 (revised)
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-- ("0111110101111011", '0', '0', '1', "0111110101111010"), -- 9 (here)
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-- ("0111110101111011", '0', '0', '1', "0111110101111010"), -- 10 (here)
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-- ("0111110101111011", '0', '0', '1', "0111110101111001"), -- 11 (here)
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-- ("0011000000111001", '0', '1', '0', "0111110101111001"), -- 12 (here)
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("0011000000111001", '0', '1', '0', "0011000000111001"), -- 13
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("0011000000111001", '1', '1', '0', "0011000000111001"), -- 14
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("0011000000111001", '1', '1', '0', "0000000000000000"), -- 15
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("0011000000111001", '0', '1', '1', "0000000000000000"), -- 16
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("0011000000111001", '0', '1', '1', "0011000000111001"), -- 17
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("0011000000111001", '1', '1', '1', "0011000000111001"), -- 18
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("0011000000111001", '1', '1', '1', "0000000000000000"), -- 19
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("0011000000111001", '0', '0', '1', "0000000000000000"), -- 20
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("0011000000111001", '0', '0', '1', "0000000000000001"), -- 21
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("0011000000111001", '1', '0', '1', "0000000000000010"), -- 22 (revised)
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-- ("0011000000111001", '1', '0', '1', "0000000000000001"), -- 22 (here)
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("0011000000111001", '1', '0', '1', "0000000000000000"), -- 23
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("0000000000000000", '0', '1', '1', "0000000000000000"), -- 24
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("0000000000000000", '0', '1', '1', "0000000000000000"), -- 25
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("0000000000000000", '0', '0', '1', "0000000000000000"), -- 26
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("0000000000000000", '0', '0', '1', "0000000000000001"), -- 27
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("0101011011001110", '1', '0', '0', "0000000000000010"), -- 28 (revised)
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-- ("0101011011001110", '1', '0', '0', "0000000000000001"), -- 28 (here)
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("0101011011001110", '1', '0', '0', "0000000000000000"), -- 29
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("0000000000000000", '1', '0', '0', "0000000000000000"), -- 30
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("0000000000000000", '0', '0', '1', "0000000000000000"), -- 31
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("0000000000000000", '0', '0', '1', "0000000000000001"), -- 32
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("0000000000000000", '0', '0', '1', "0000000000000010"), -- 33
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("0000000000000000", '0', '0', '1', "0000000000000011"), -- 34
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("0000000000000000", '0', '0', '1', "0000000000000100"), -- 35
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("0000000000000000", '0', '0', '1', "0000000000000101") -- 36
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);
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begin
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-- Check each pattern.
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for i in patterns'range loop
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-- Set the inputs.
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d <= patterns(i).d;
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reset <= patterns(i).reset;
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load <= patterns(i).load;
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inc <= patterns(i).inc;
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wait for 0.25 ns;
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-- Check the outputs.
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assert cout = patterns(i).cout
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report "bad counter" severity error;
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wait for 0.75 ns;
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end loop;
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-- End the clock
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finish <= '1';
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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end process;
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end pc_tb_arch;
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