64 lines
2.4 KiB
VHDL
64 lines
2.4 KiB
VHDL
-- (C) Copyright Collin J. Doering 2015
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- File: ram64.vhdl
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-- Author: Collin J. Doering <collin.doering@rekahsoft.ca>
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-- Date: May 22, 2015
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity ram64 is
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port (d : in std_logic_vector(15 downto 0);
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load : in std_logic;
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address : in std_logic_vector(5 downto 0);
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clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end ram64;
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architecture ram64_arch of ram64 is
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component ram8
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port (d : in std_logic_vector(15 downto 0);
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load : in std_logic;
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address : in std_logic_vector(2 downto 0);
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clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end component;
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component dmux8way
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port (cin : in std_logic;
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sel : in std_logic_vector(2 downto 0);
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a, b, c, d, e, f, g, h : out std_logic);
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end component;
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component mux8way16
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port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
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sel : in std_logic_vector(2 downto 0);
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cout : out std_logic_vector(15 downto 0));
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end component;
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signal ramLoad : std_logic_vector(7 downto 0);
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type ramoutT is array (7 downto 0) of std_logic_vector(15 downto 0);
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signal ramOut : ramoutT;
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begin
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dmux8way_0: dmux8way port map (load, address(2 downto 0), ramLoad(0), ramLoad(1), ramLoad(2), ramLoad(3), ramLoad(4), ramLoad(5), ramLoad(6), ramLoad(7));
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ram: for i in ramLoad'range generate
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ram8_i: ram8 port map (d, ramLoad(i), address(5 downto 3), clk, ramOut(i));
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end generate;
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mux8way16_0: mux8way16 port map (ramOut(0), ramOut(1), ramOut(2), ramOut(3), ramOut(4), ramOut(5), ramOut(6), ramOut(7), address(2 downto 0), cout);
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end ram64_arch;
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