194 lines
3.9 KiB
Plaintext
194 lines
3.9 KiB
Plaintext
v 20130925 2
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C 40000 40000 0 0 0 title-B.sym
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C 46900 45200 1 0 0 EMBEDDED7400-1.sym
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[
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L 47200 45400 47200 46000 3 0 0 0 -1 -1
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L 47200 46000 47600 46000 3 0 0 0 -1 -1
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L 47200 45400 47600 45400 3 0 0 0 -1 -1
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A 47600 45700 300 270 180 3 0 0 0 -1 -1
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V 47950 45700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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P 48000 45700 48200 45700 1 0 1
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{
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T 48000 45750 5 8 1 1 0 0 1
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pinnumber=3
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T 48000 45650 5 8 0 1 0 2 1
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pinseq=3
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T 47850 45700 9 8 0 1 0 6 1
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pinlabel=Y
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T 47850 45700 5 8 0 1 0 8 1
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pintype=out
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}
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P 47200 45500 46900 45500 1 0 1
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{
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T 47100 45550 5 8 1 1 0 6 1
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pinnumber=2
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T 47100 45450 5 8 0 1 0 8 1
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pinseq=2
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T 47250 45500 9 8 0 1 0 0 1
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pinlabel=B
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T 47250 45500 5 8 0 1 0 2 1
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pintype=in
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}
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P 47200 45900 46900 45900 1 0 1
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{
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T 47100 45950 5 8 1 1 0 6 1
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pinnumber=1
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T 47100 45850 5 8 0 1 0 8 1
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pinseq=1
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T 47250 45900 9 8 0 1 0 0 1
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pinlabel=A
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T 47250 45900 5 8 0 1 0 2 1
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pintype=in
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}
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T 47200 45200 9 8 1 0 0 0 1
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7400
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T 47400 46100 5 10 0 0 0 0 1
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device=7400
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T 47400 46300 5 10 0 0 0 0 1
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slot=1
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T 47400 46500 5 10 0 0 0 0 1
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numslots=4
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T 47400 46700 5 10 0 0 0 0 1
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slotdef=1:1,2,3
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T 47400 46900 5 10 0 0 0 0 1
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slotdef=2:4,5,6
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T 47400 47100 5 10 0 0 0 0 1
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slotdef=3:9,10,8
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T 47400 47300 5 10 0 0 0 0 1
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slotdef=4:12,13,11
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T 47200 46100 8 10 0 1 0 0 1
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refdes=U?
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T 47400 47450 5 10 0 0 0 0 1
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footprint=DIP14
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T 47400 47650 5 10 0 0 0 0 1
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description=4 NAND gates with 2 inputs
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T 47400 48050 5 10 0 0 0 0 1
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net=Vcc:14
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T 47400 48250 5 10 0 0 0 0 1
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net=GND:7
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T 47400 47850 5 10 0 0 0 0 1
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documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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]
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{
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T 47400 46100 5 10 0 0 0 0 1
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device=7400
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T 47400 47450 5 10 0 0 0 0 1
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footprint=DIP14
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T 47200 46100 5 10 1 1 0 0 1
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refdes=U1
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}
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C 48500 45200 1 0 0 EMBEDDED7400-1.sym
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[
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L 48800 45400 48800 46000 3 0 0 0 -1 -1
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L 48800 46000 49200 46000 3 0 0 0 -1 -1
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L 48800 45400 49200 45400 3 0 0 0 -1 -1
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A 49200 45700 300 270 180 3 0 0 0 -1 -1
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V 49550 45700 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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P 49600 45700 49800 45700 1 0 1
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{
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T 49600 45750 5 8 1 1 0 0 1
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pinnumber=3
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T 49600 45650 5 8 0 1 0 2 1
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pinseq=3
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T 49450 45700 9 8 0 1 0 6 1
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pinlabel=Y
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T 49450 45700 5 8 0 1 0 8 1
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pintype=out
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}
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P 48800 45500 48500 45500 1 0 1
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{
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T 48700 45550 5 8 1 1 0 6 1
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pinnumber=2
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T 48700 45450 5 8 0 1 0 8 1
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pinseq=2
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T 48850 45500 9 8 0 1 0 0 1
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pinlabel=B
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T 48850 45500 5 8 0 1 0 2 1
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pintype=in
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}
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P 48800 45900 48500 45900 1 0 1
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{
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T 48700 45950 5 8 1 1 0 6 1
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pinnumber=1
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T 48700 45850 5 8 0 1 0 8 1
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pinseq=1
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T 48850 45900 9 8 0 1 0 0 1
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pinlabel=A
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T 48850 45900 5 8 0 1 0 2 1
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pintype=in
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}
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T 48800 45200 9 8 1 0 0 0 1
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7400
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T 49000 46100 5 10 0 0 0 0 1
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device=7400
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T 49000 46300 5 10 0 0 0 0 1
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slot=1
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T 49000 46500 5 10 0 0 0 0 1
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numslots=4
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T 49000 46700 5 10 0 0 0 0 1
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slotdef=1:1,2,3
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T 49000 46900 5 10 0 0 0 0 1
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slotdef=2:4,5,6
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T 49000 47100 5 10 0 0 0 0 1
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slotdef=3:9,10,8
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T 49000 47300 5 10 0 0 0 0 1
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slotdef=4:12,13,11
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T 48800 46100 8 10 0 1 0 0 1
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refdes=U?
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T 49000 47450 5 10 0 0 0 0 1
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footprint=DIP14
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T 49000 47650 5 10 0 0 0 0 1
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description=4 NAND gates with 2 inputs
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T 49000 48050 5 10 0 0 0 0 1
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net=Vcc:14
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T 49000 48250 5 10 0 0 0 0 1
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net=GND:7
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T 49000 47850 5 10 0 0 0 0 1
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documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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]
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{
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T 49000 46100 5 10 0 0 0 0 1
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device=7400
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T 49000 47450 5 10 0 0 0 0 1
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footprint=DIP14
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T 48800 46100 5 10 1 1 0 0 1
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refdes=U2
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}
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N 48500 45500 48500 45900 4
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N 48200 45700 48500 45700 4
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T 50100 40700 9 10 1 0 0 0 1
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And gate contructed from nand gates
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P 46900 45900 46700 45900 1 0 0
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{
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T 46900 45900 5 10 0 0 0 0 1
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pintype=unknown
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T 46645 45895 5 10 1 1 0 6 1
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pinlabel=a
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T 46795 45945 5 10 0 1 0 0 1
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pinnumber=0
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T 46900 45900 5 10 0 0 0 0 1
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pinseq=0
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}
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P 46900 45500 46700 45500 1 0 0
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{
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T 46900 45500 5 10 0 0 0 0 1
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pintype=unknown
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T 46645 45495 5 10 1 1 0 6 1
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pinlabel=b
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T 46795 45545 5 10 0 1 0 0 1
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pinnumber=1
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T 46900 45500 5 10 0 0 0 0 1
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pinseq=0
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}
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P 49800 45700 50000 45700 1 0 0
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{
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T 49800 45700 5 10 0 0 0 0 1
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pintype=unknown
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T 50055 45695 5 10 1 1 0 0 1
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pinlabel=cout
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T 49905 45745 5 10 0 1 0 6 1
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pinnumber=0
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T 49800 45700 5 10 0 0 0 0 1
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pinseq=0
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}
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