273 lines
5.5 KiB
Plaintext
273 lines
5.5 KiB
Plaintext
v 20130925 2
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C 40000 40000 0 0 0 title-B.sym
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C 47300 45600 1 0 0 EMBEDDED7400-1.sym
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[
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L 47600 45800 47600 46400 3 0 0 0 -1 -1
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L 47600 46400 48000 46400 3 0 0 0 -1 -1
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L 47600 45800 48000 45800 3 0 0 0 -1 -1
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A 48000 46100 300 270 180 3 0 0 0 -1 -1
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V 48350 46100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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P 48400 46100 48600 46100 1 0 1
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{
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T 48400 46150 5 8 1 1 0 0 1
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pinnumber=3
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T 48400 46050 5 8 0 1 0 2 1
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pinseq=3
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T 48250 46100 9 8 0 1 0 6 1
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pinlabel=Y
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T 48250 46100 5 8 0 1 0 8 1
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pintype=out
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}
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P 47600 45900 47300 45900 1 0 1
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{
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T 47500 45950 5 8 1 1 0 6 1
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pinnumber=2
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T 47500 45850 5 8 0 1 0 8 1
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pinseq=2
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T 47650 45900 9 8 0 1 0 0 1
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pinlabel=B
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T 47650 45900 5 8 0 1 0 2 1
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pintype=in
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}
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P 47600 46300 47300 46300 1 0 1
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{
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T 47500 46350 5 8 1 1 0 6 1
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pinnumber=1
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T 47500 46250 5 8 0 1 0 8 1
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pinseq=1
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T 47650 46300 9 8 0 1 0 0 1
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pinlabel=A
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T 47650 46300 5 8 0 1 0 2 1
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pintype=in
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}
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T 47600 45600 9 8 1 0 0 0 1
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7400
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T 47800 46500 5 10 0 0 0 0 1
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device=7400
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T 47800 46700 5 10 0 0 0 0 1
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slot=1
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T 47800 46900 5 10 0 0 0 0 1
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numslots=4
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T 47800 47100 5 10 0 0 0 0 1
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slotdef=1:1,2,3
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T 47800 47300 5 10 0 0 0 0 1
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slotdef=2:4,5,6
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T 47800 47500 5 10 0 0 0 0 1
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slotdef=3:9,10,8
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T 47800 47700 5 10 0 0 0 0 1
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slotdef=4:12,13,11
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T 47600 46500 8 10 0 1 0 0 1
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refdes=U?
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T 47800 47850 5 10 0 0 0 0 1
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footprint=DIP14
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T 47800 48050 5 10 0 0 0 0 1
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description=4 NAND gates with 2 inputs
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T 47800 48450 5 10 0 0 0 0 1
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net=Vcc:14
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T 47800 48650 5 10 0 0 0 0 1
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net=GND:7
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T 47800 48250 5 10 0 0 0 0 1
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documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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]
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{
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T 47800 46500 5 10 0 0 0 0 1
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device=7400
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T 47800 47850 5 10 0 0 0 0 1
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footprint=DIP14
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T 47600 46500 5 10 1 1 0 0 1
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refdes=U1
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}
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C 47300 44500 1 0 0 EMBEDDED7400-1.sym
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[
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L 47600 44700 47600 45300 3 0 0 0 -1 -1
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L 47600 45300 48000 45300 3 0 0 0 -1 -1
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L 47600 44700 48000 44700 3 0 0 0 -1 -1
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A 48000 45000 300 270 180 3 0 0 0 -1 -1
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V 48350 45000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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P 48400 45000 48600 45000 1 0 1
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{
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T 48400 45050 5 8 1 1 0 0 1
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pinnumber=3
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T 48400 44950 5 8 0 1 0 2 1
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pinseq=3
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T 48250 45000 9 8 0 1 0 6 1
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pinlabel=Y
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T 48250 45000 5 8 0 1 0 8 1
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pintype=out
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}
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P 47600 44800 47300 44800 1 0 1
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{
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T 47500 44850 5 8 1 1 0 6 1
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pinnumber=2
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T 47500 44750 5 8 0 1 0 8 1
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pinseq=2
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T 47650 44800 9 8 0 1 0 0 1
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pinlabel=B
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T 47650 44800 5 8 0 1 0 2 1
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pintype=in
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}
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P 47600 45200 47300 45200 1 0 1
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{
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T 47500 45250 5 8 1 1 0 6 1
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pinnumber=1
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T 47500 45150 5 8 0 1 0 8 1
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pinseq=1
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T 47650 45200 9 8 0 1 0 0 1
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pinlabel=A
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T 47650 45200 5 8 0 1 0 2 1
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pintype=in
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}
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T 47600 44500 9 8 1 0 0 0 1
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7400
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T 47800 45400 5 10 0 0 0 0 1
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device=7400
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T 47800 45600 5 10 0 0 0 0 1
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slot=1
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T 47800 45800 5 10 0 0 0 0 1
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numslots=4
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T 47800 46000 5 10 0 0 0 0 1
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slotdef=1:1,2,3
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T 47800 46200 5 10 0 0 0 0 1
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slotdef=2:4,5,6
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T 47800 46400 5 10 0 0 0 0 1
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slotdef=3:9,10,8
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T 47800 46600 5 10 0 0 0 0 1
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slotdef=4:12,13,11
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T 47600 45400 8 10 0 1 0 0 1
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refdes=U?
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T 47800 46750 5 10 0 0 0 0 1
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footprint=DIP14
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T 47800 46950 5 10 0 0 0 0 1
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description=4 NAND gates with 2 inputs
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T 47800 47350 5 10 0 0 0 0 1
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net=Vcc:14
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T 47800 47550 5 10 0 0 0 0 1
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net=GND:7
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T 47800 47150 5 10 0 0 0 0 1
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documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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]
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{
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T 47800 45400 5 10 0 0 0 0 1
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device=7400
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T 47800 46750 5 10 0 0 0 0 1
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footprint=DIP14
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T 47600 45400 5 10 1 1 0 0 1
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refdes=U2
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}
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C 48600 45100 1 0 0 EMBEDDED7400-1.sym
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[
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L 48900 45300 48900 45900 3 0 0 0 -1 -1
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L 48900 45900 49300 45900 3 0 0 0 -1 -1
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L 48900 45300 49300 45300 3 0 0 0 -1 -1
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A 49300 45600 300 270 180 3 0 0 0 -1 -1
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V 49650 45600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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P 49700 45600 49900 45600 1 0 1
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{
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T 49700 45650 5 8 1 1 0 0 1
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pinnumber=3
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T 49700 45550 5 8 0 1 0 2 1
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pinseq=3
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T 49550 45600 9 8 0 1 0 6 1
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pinlabel=Y
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T 49550 45600 5 8 0 1 0 8 1
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pintype=out
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}
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P 48900 45400 48600 45400 1 0 1
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{
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T 48800 45450 5 8 1 1 0 6 1
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pinnumber=2
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T 48800 45350 5 8 0 1 0 8 1
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pinseq=2
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T 48950 45400 9 8 0 1 0 0 1
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pinlabel=B
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T 48950 45400 5 8 0 1 0 2 1
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pintype=in
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}
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P 48900 45800 48600 45800 1 0 1
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{
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T 48800 45850 5 8 1 1 0 6 1
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pinnumber=1
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T 48800 45750 5 8 0 1 0 8 1
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pinseq=1
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T 48950 45800 9 8 0 1 0 0 1
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pinlabel=A
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T 48950 45800 5 8 0 1 0 2 1
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pintype=in
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}
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T 48900 45100 9 8 1 0 0 0 1
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7400
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T 49100 46000 5 10 0 0 0 0 1
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device=7400
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T 49100 46200 5 10 0 0 0 0 1
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slot=1
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T 49100 46400 5 10 0 0 0 0 1
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numslots=4
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T 49100 46600 5 10 0 0 0 0 1
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slotdef=1:1,2,3
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T 49100 46800 5 10 0 0 0 0 1
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slotdef=2:4,5,6
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T 49100 47000 5 10 0 0 0 0 1
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slotdef=3:9,10,8
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T 49100 47200 5 10 0 0 0 0 1
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slotdef=4:12,13,11
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T 48900 46000 8 10 0 1 0 0 1
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refdes=U?
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T 49100 47350 5 10 0 0 0 0 1
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footprint=DIP14
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T 49100 47550 5 10 0 0 0 0 1
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description=4 NAND gates with 2 inputs
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T 49100 47950 5 10 0 0 0 0 1
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net=Vcc:14
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T 49100 48150 5 10 0 0 0 0 1
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net=GND:7
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T 49100 47750 5 10 0 0 0 0 1
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documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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]
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{
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T 49100 46000 5 10 0 0 0 0 1
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device=7400
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T 49100 47350 5 10 0 0 0 0 1
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footprint=DIP14
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T 48900 46000 5 10 1 1 0 0 1
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refdes=U3
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}
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N 47300 45900 47300 46300 4
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N 47300 44800 47300 45200 4
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N 48600 45000 48600 45400 4
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N 48600 46100 48600 45800 4
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T 50100 40700 9 10 1 0 0 0 1
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Or Gate Contructed from Nand Gates
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P 49900 45600 50200 45600 1 0 0
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{
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T 49900 45600 5 10 0 0 0 0 1
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pintype=unknown
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T 50255 45595 5 10 1 1 0 0 1
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pinlabel=cout
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T 50105 45645 5 10 0 1 0 6 1
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pinnumber=0
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T 49900 45600 5 10 0 0 0 0 1
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pinseq=0
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}
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P 47300 46100 47000 46100 1 0 0
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{
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T 47300 46100 5 10 0 0 0 0 1
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pintype=unknown
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T 46945 46095 5 10 1 1 0 6 1
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pinlabel=a
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T 47095 46145 5 10 0 1 0 0 1
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pinnumber=0
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T 47300 46100 5 10 0 0 0 0 1
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pinseq=0
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}
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P 47300 45000 47000 45000 1 0 0
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{
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T 47300 45000 5 10 0 0 0 0 1
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pintype=unknown
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T 46945 44995 5 10 1 1 0 6 1
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pinlabel=b
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T 47095 45045 5 10 1 1 0 0 1
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pinnumber=0
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T 47300 45000 5 10 0 0 0 0 1
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pinseq=0
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}
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