An implementation of the Hack computer in VHDL based off of the Nand to Tetris course.
Collin J. Doering
7e6bc05a9d
Finished testing the cpu implementation. The test data from the nand to tetris course was modified slightly to fit different timing in this simulation. Specifically, every two rows given in the test data refer to part way though the 'low' part of the clock cycle, then the 'high' part of the cycle respectively. To keep things simple all synchronous test benches in this project have set sample inputs, waited 25 ps then checked the given sample output; then the simulation is paused for the remaining cycle (750 ps); this makes for a cycle period of 1 ns. Setting and testing the given test data all happens before the clock goes 'high' and thus each row in the test data given in the test bench refers to the same time. Thus if some piece of data is stored in cycle 'a' then in cycle 'a + 1' that data is guarantied to be in place. Example: Consider this simple hack assembly program. @3 // 0000000000000011 D=A // 1110110000010000 D=D+A // 1110000010010000 This program can is executed as follows (ignoring reading from ROM): Load 3 into register A in time step 1 (doesn't get synchronized until the clock goes 'high', so A will not be read as 3 until the next time step). Set D=A=3 in time step 2, similarly to the first step, this value will not be synchronized until the following time step. Finally set D=D+A=3+3, which again, won't appear in the D register until the following time step. Signed-off-by: Collin J. Doering <collin.doering@rekahsoft.ca> |
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| .gitignore | ||
| gpl.txt | ||