17 lines
363 B
VHDL
17 lines
363 B
VHDL
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity clock is
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port (finish : in std_logic;
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cout : out std_logic);
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end clock;
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architecture clock_arch of clock is
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signal clk: std_logic := '0';
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begin
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clk <= '0' when finish = '1' else
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'1' after 0.5 ns when clk = '0' else
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'0' after 0.5 ns when clk = '1';
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cout <= clk;
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end clock_arch;
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