Collin J. Doering 6ab2badb26 Initial commit ... Contains vhdl code and test benches for the following chips: - adder - add16 - alu - dff - dbit - dregister - dmux - dmux4way - dmux8way - mux - mux16 - mux4way16 - mux8way16 - pc - ram8 - ram64 - ram512 - ram4k - ram16k For simulation of sequential chips, a clock must be used; this is implemented as 'src/clock.vhdl' with accompanying test bench 'src/clock_tb.vhdl'. 'src/wave/gktw' contains gtkwave save files for viewing the output of the various test benches. The 'schematics' directory contains schematics of the various chips (incomplete). Things not yet completed: - weird issue with 'src/pc_tb.vhdl'; that is, the test data from the "nand to tetris" course doesn't fit the simulation but the simulation appears to be correct (by inspection). - cpu chip - build system (currently things can built by hand using ghdl as follows) To build the various chips and their respective test benches, use ghdl like so: $ cd src $ ghdl -i --workdir=work *.vhdl $ ghdl -m --workdir=work <chip_name>_tb $ ghdl -r <chip_name>_tb --vcd=wave/vcd/<chip_name>.vcd You can then view the wave output file in 'src/wave/vcd/<chip_name>.vcd'.		2015-05-21 15:12:01 -04:00
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wave	Initial commit	2015-05-21 15:12:01 -04:00
work	Initial commit	2015-05-21 15:12:01 -04:00
DFF.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
DFF_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
add16.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
add16_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
adder.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
adder_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
alu.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
alu_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
clock.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
clock_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
dbit.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
dbit_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
dmux.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
dmux4way.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
dmux4way_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
dmux8way.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
dmux8way_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
dmux_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
dregister.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
dregister_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
mux.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
mux4way16.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
mux4way16_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
mux8way16.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
mux8way16_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
mux16.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
mux16_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
mux_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
pc.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
pc_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
ram4k.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
ram4k_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
ram8.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
ram8_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
ram16k.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
ram16k_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
ram64.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
ram64_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
ram512.vhdl	Initial commit	2015-05-21 15:12:01 -04:00
ram512_tb.vhdl	Initial commit	2015-05-21 15:12:01 -04:00