13 lines
223 B
VHDL
13 lines
223 B
VHDL
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity mux is
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port (a, b, sel : in std_logic;
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cout : out std_logic);
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end mux;
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architecture mux_arch of mux is
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begin
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cout <= a when sel='0' else b;
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end mux_arch;
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