14 lines
292 B
VHDL
14 lines
292 B
VHDL
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity mux16 is
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port (a, b : in std_logic_vector(15 downto 0);
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sel : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end mux16;
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architecture mux16_arch of mux16 is
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begin
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cout <= a when sel='0' else b;
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end mux16_arch;
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