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hack/schematics/and.sch

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Initial commit Contains vhdl code and test benches for the following chips: - adder - add16 - alu - dff - dbit - dregister - dmux - dmux4way - dmux8way - mux - mux16 - mux4way16 - mux8way16 - pc - ram8 - ram64 - ram512 - ram4k - ram16k For simulation of sequential chips, a clock must be used; this is implemented as 'src/clock.vhdl' with accompanying test bench 'src/clock_tb.vhdl'. 'src/wave/gktw' contains gtkwave save files for viewing the output of the various test benches. The 'schematics' directory contains schematics of the various chips (incomplete). Things not yet completed: - weird issue with 'src/pc_tb.vhdl'; that is, the test data from the "nand to tetris" course doesn't fit the simulation but the simulation appears to be correct (by inspection). - cpu chip - build system (currently things can built by hand using ghdl as follows) To build the various chips and their respective test benches, use ghdl like so: $ cd src $ ghdl -i --workdir=work *.vhdl $ ghdl -m --workdir=work <chip_name>_tb $ ghdl -r <chip_name>_tb --vcd=wave/vcd/<chip_name>.vcd You can then view the wave output file in 'src/wave/vcd/<chip_name>.vcd'.
2015-05-21 19:12:01 +00:00
v 20130925 2
C 40000 40000 0 0 0 title-B.sym
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documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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T 48800 46100 8 10 0 1 0 0 1
refdes=U?
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footprint=DIP14
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net=Vcc:14
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net=GND:7
T 49000 47850 5 10 0 0 0 0 1
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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And gate contructed from nand gates
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