The test bench 'cpu_tb.vhdl' currently fails for almost all inputs. Though from
analysis of the vcd output, everything seems to be working correctly. It
seems that the compare data from the nand to tetris course for
synchronized circuits/chips does not behave nicely with this simulation
because it assumes two clock cycles is one discreet time
unit (tick-tock) whereas in this simulation every pulse of the
clock (1 ns period) acts as a single discreet time unit. This however
still needs to be investigated and also is an issue in the
implementation of 'pc_tb.vhdl'.
Signed-off-by: Collin J. Doering <collin.doering@rekahsoft.ca>
