The test bench 'cpu_tb.vhdl' currently fails for almost all inputs. Though from
analysis of the vcd output, everything seems to be working correctly. It
seems that the compare data from the nand to tetris course for
synchronized circuits/chips does not behave nicely with this simulation
because it assumes two clock cycles is one discreet time
unit (tick-tock) whereas in this simulation every pulse of the
clock (1 ns period) acts as a single discreet time unit. This however
still needs to be investigated and also is an issue in the
implementation of 'pc_tb.vhdl'.
Signed-off-by: Collin J. Doering <collin.doering@rekahsoft.ca>
Contains vhdl code and test benches for the following chips:
- adder
- add16
- alu
- dff
- dbit
- dregister
- dmux
- dmux4way
- dmux8way
- mux
- mux16
- mux4way16
- mux8way16
- pc
- ram8
- ram64
- ram512
- ram4k
- ram16k
For simulation of sequential chips, a clock must be used; this is
implemented as 'src/clock.vhdl' with accompanying test bench
'src/clock_tb.vhdl'.
'src/wave/gktw' contains gtkwave save files for viewing the output of
the various test benches.
The 'schematics' directory contains schematics of the various
chips (incomplete).
Things not yet completed:
- weird issue with 'src/pc_tb.vhdl'; that is, the test data from the
"nand to tetris" course doesn't fit the simulation but the simulation
appears to be correct (by inspection).
- cpu chip
- build system (currently things can built by hand using ghdl as
follows)
To build the various chips and their respective test benches, use ghdl
like so:
$ cd src
$ ghdl -i --workdir=work *.vhdl
$ ghdl -m --workdir=work <chip_name>_tb
$ ghdl -r <chip_name>_tb --vcd=wave/vcd/<chip_name>.vcd
You can then view the wave output file in
'src/wave/vcd/<chip_name>.vcd'.
