20 lines
351 B
VHDL
20 lines
351 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity DFF is
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port (d, clk : in std_logic;
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cout : out std_logic);
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end DFF;
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architecture DFF_arch of DFF is
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signal coutFst : std_logic := '0';
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begin
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cout <= coutFst;
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dff: process(clk)
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begin
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if (rising_edge(clk)) then
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coutFst <= d;
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end if;
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end process dff;
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end DFF_arch;
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