65 lines
2.5 KiB
VHDL
65 lines
2.5 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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-- A testbench has no ports.
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entity add16_tb is
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end add16_tb;
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architecture add16_tb_arch of add16_tb is
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-- Declaration of the component that will be instantiated.
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component add16
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port (a, b : std_logic_vector(15 downto 0); cout : out std_logic_vector(15 downto 0));
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end component;
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-- Specifies which entity is bound with the component.
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for add16_0: add16 use entity work.add16;
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signal a, b, cout : std_logic_vector(15 downto 0);
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begin
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-- Component instantiation.
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add16_0: add16 port map (a, b, cout);
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-- This process does the real job.
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process
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type pattern_type is record
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-- The inputs of the add16.
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a, b : std_logic_vector(15 downto 0);
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-- The expected output of the add16.
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cout : std_logic_vector(15 downto 0);
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end record;
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-- The patterns to apply.
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type pattern_array is array (natural range <>) of pattern_type;
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constant patterns : pattern_array :=
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(("0000000000000000", "0000000000000000", "0000000000000000"),
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("0000000000000001", "0000000000000000", "0000000000000001"),
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("0000000000000001", "0000000000000001", "0000000000000010"),
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("0000000000000010", "0000000000000001", "0000000000000011"),
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("0000000000000011", "0000000000000001", "0000000000000100"),
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("0000000000000010", "0000000000000100", "0000000000000110"),
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("1000000000000000", "1000000000000000", "0000000000000000"),
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("1100000000000011", "1100000000000111", "1000000000001010"),
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-- Tests given by Nand to tetris course
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("0000000000000000", "0000000000000000", "0000000000000000"),
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("0000000000000000", "1111111111111111", "1111111111111111"),
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("1111111111111111", "1111111111111111", "1111111111111110"),
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("1010101010101010", "0101010101010101", "1111111111111111"),
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("0011110011000011", "0000111111110000", "0100110010110011"),
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("0001001000110100", "1001100001110110", "1010101010101010"));
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begin
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-- Check each pattern.
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for i in patterns'range loop
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-- Set the inputs.
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a <= patterns(i).a;
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b <= patterns(i).b;
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cout <= patterns(i).cout;
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-- Wait for the results.
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wait for 1 ns;
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-- Check the outputs.
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assert cout = patterns(i).cout
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report "incorrect addition" severity error;
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end loop;
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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end process;
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end add16_tb_arch;
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