18 lines
421 B
VHDL
18 lines
421 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity adder is
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-- i0, i1 and the carry-in ci are inputs of the adder.
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-- s is the sum output, co is the carry-out.
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port (a, b, ci : in std_logic;
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s, co : out std_logic);
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end adder;
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architecture adder_arch of adder is
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begin
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-- Compute the sum.
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s <= a xor b xor ci;
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-- Compute the carry.
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co <= (a and b) or (a and ci) or (b and ci);
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end adder_arch;
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