59 lines
1.8 KiB
VHDL
59 lines
1.8 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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-- A testbench has no ports.
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entity adder_tb is
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end adder_tb;
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architecture adder_tb_arch of adder_tb is
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-- Declaration of the component that will be instantiated.
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component adder
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port (a, b, ci : in std_logic; s, co : out std_logic);
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end component;
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-- Specifies which entity is bound with the component.
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for adder_0: adder use entity work.adder;
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signal a, b, ci, s, co : std_logic;
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begin
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-- Component instantiation.
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adder_0: adder port map (a, b, ci, s, co);
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-- This process does the real job.
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process
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type pattern_type is record
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-- The inputs of the adder.
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a, b, ci : std_logic;
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-- The expected outputs of the adder.
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s, co : std_logic;
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end record;
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-- The patterns to apply.
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type pattern_array is array (natural range <>) of pattern_type;
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constant patterns : pattern_array :=
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(('0', '0', '0', '0', '0'),
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('0', '0', '1', '1', '0'),
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('0', '1', '0', '1', '0'),
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('0', '1', '1', '0', '1'),
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('1', '0', '0', '1', '0'),
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('1', '0', '1', '0', '1'),
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('1', '1', '0', '0', '1'),
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('1', '1', '1', '1', '1'));
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begin
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-- Check each pattern.
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for i in patterns'range loop
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-- Set the inputs.
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a <= patterns(i).a;
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b <= patterns(i).b;
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ci <= patterns(i).ci;
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-- Wait for the results.
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wait for 1 ns;
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-- Check the outputs.
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assert s = patterns(i).s
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report "bad sum value" severity error;
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assert co = patterns(i).co
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report "bad carray out value" severity error;
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end loop;
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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end process;
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end adder_tb_arch;
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