41 lines
1.5 KiB
VHDL
41 lines
1.5 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity alu is
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port (x, y : in std_logic_vector(15 downto 0);
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zx, nx, zy, ny, f, no : in std_logic;
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cout : out std_logic_vector(15 downto 0);
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zr, ng : out std_logic);
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end alu;
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architecture alu_arch of alu is
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component mux16
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port (a, b : in std_logic_vector(15 downto 0); sel : in std_logic; cout : out std_logic_vector(15 downto 0));
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end component;
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component add16
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port (a, b : in std_logic_vector(15 downto 0); cout : out std_logic_vector(15 downto 0));
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end component;
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signal zeroX, zeroXNot, negateX, zeroY, zeroYNot, negateY, negateXAndnegateY, bitwiseAnd, addition, whichF, whichFNot, negateOut : std_logic_vector(15 downto 0);
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constant zeros : std_logic_vector(15 downto 0) := "0000000000000000";
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begin
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zeroXMux: mux16 port map (x, zeros, zx, zeroX);
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zeroXNot <= not zeroX;
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negateXMux: mux16 port map (zeroX, zeroXNot, nx, negateX);
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zeroYMux: mux16 port map (y, zeros, zy, zeroY);
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zeroYNot <= not zeroY;
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negateYMux: mux16 port map (zeroY, zeroYNot, ny, negateY);
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fAdd: add16 port map (negateX, negateY, addition);
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negateXAndNegateY <= negateX and negateY;
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whichFMux: mux16 port map (negateXAndNegateY, addition, f, whichF);
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whichFNot <= not whichF;
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negateOutMux: mux16 port map (whichF, whichFNot, no, negateOut);
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cout <= negateOut;
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zr <= '1' when negateOut = zeros else '0';
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ng <= negateOut(15);
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end alu_arch;
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