23 lines
533 B
VHDL
23 lines
533 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity dbit is
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port (d, load, clk : in std_logic;
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cout : out std_logic);
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end dbit;
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architecture dbit_arch of dbit is
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component mux
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port (a, b, sel : in std_logic; cout : out std_logic);
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end component;
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component dff
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port (d, clk : in std_logic; cout : out std_logic);
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end component;
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signal dffOut, muxOut : std_logic;
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begin
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MUX_0: mux port map (dffOut, d, load, muxOut);
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DFF_0: dff port map (muxOut, clk, dffOut);
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cout <= dffOut;
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end dbit_arch;
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