273 lines
7.1 KiB
VHDL
273 lines
7.1 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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-- A testbench has no ports.
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entity dbit_tb is
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end dbit_tb;
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architecture dbit_tb_arch of dbit_tb is
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-- Declaration of the component that will be instantiated.
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component dbit
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port (d, load, clk : in std_logic; cout : out std_logic);
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end component;
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-- Declaration of the clock
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component Clock
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port (finish : in std_logic;
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cout : out std_logic);
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end component;
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-- Specifies which entity is bound with the component.
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for dbit_0: dbit use entity work.dbit;
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signal d, load, finish, clk, cout : std_logic;
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begin
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-- Component instantiation.
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OSC_CLK: Clock port map (finish, clk);
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dbit_0: dbit port map (d, load, clk, cout);
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-- This process does the real job.
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process
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type pattern_type is record
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-- The inputs of the dbit.
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d, load : std_logic;
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-- The output of the dbit.
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cout : std_logic;
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end record;
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-- The patterns to apply.
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type pattern_array is array (natural range <>) of pattern_type;
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constant patterns : pattern_array :=
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(('0', '0', '0'),
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('0', '0', '0'),
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('0', '0', '0'),
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('0', '1', '0'),
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('0', '1', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '1', '0'),
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('1', '1', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('1', '0', '1'),
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('1', '0', '1'),
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('0', '1', '1'),
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('0', '1', '0'),
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('1', '1', '0'),
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('1', '1', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '0', '1'),
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('0', '1', '1'),
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('0', '1', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'),
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('1', '0', '0'));
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begin
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-- Check each pattern.
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for i in patterns'range loop
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-- Set the inputs.
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d <= patterns(i).d;
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load <= patterns(i).load;
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wait for 0.25 ns;
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-- Check the outputs.
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assert cout = patterns(i).cout
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report "bad data; nothing remembered" severity error;
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wait for 0.75 ns;
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end loop;
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-- End the clock
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finish <= '1';
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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end process;
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end dbit_tb_arch;
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