22 lines
550 B
VHDL
22 lines
550 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity dmux4way is
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port (cin : in std_logic;
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sel : in std_logic_vector(1 downto 0);
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a, b, c, d : out std_logic);
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end dmux4way;
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architecture dmux4way_arch of dmux4way is
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component dmux
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port (cin, sel : in std_logic;
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a, b : out std_logic);
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end component;
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signal dm1, dm2 : std_logic;
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begin
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dmux_0: dmux port map (cin, sel(1), dm1, dm2);
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dmux_1: dmux port map (dm1, sel(0), a, b);
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dmux_2: dmux port map (dm2, sel(0), c, d);
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end dmux4way_arch;
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