64 lines
2.2 KiB
VHDL
64 lines
2.2 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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-- A testbench has no ports.
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entity dmux4way_tb is
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end dmux4way_tb;
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architecture dmux4way_tb_arch of dmux4way_tb is
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-- Declaration of the component that will be instantiated.
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component dmux4way
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port (cin : in std_logic; sel : in std_logic_vector(1 downto 0); a, b, c, d : out std_logic);
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end component;
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-- Specifies which entity is bound with the component.
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for dmux4way_0: dmux4way use entity work.dmux4way;
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signal cin, a, b, c, d : std_logic;
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signal sel : std_logic_vector(1 downto 0);
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begin
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-- Component instantiation.
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dmux4way_0: dmux4way port map (cin, sel, a, b, c, d);
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-- This process does the real job.
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process
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type pattern_type is record
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-- The inputs of the dmux4way.
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cin : std_logic;
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sel : std_logic_vector(1 downto 0);
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-- The expected outputs of the dmux4way.
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a, b, c, d : std_logic;
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end record;
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-- The patterns to apply.
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type pattern_array is array (natural range <>) of pattern_type;
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constant patterns : pattern_array :=
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(('0', "00", '0', '0', '0', '0'),
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('0', "01", '0', '0', '0', '0'),
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('0', "10", '0', '0', '0', '0'),
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('0', "11", '0', '0', '0', '0'),
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('1', "00", '1', '0', '0', '0'),
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('1', "01", '0', '1', '0', '0'),
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('1', "10", '0', '0', '1', '0'),
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('1', "11", '0', '0', '0', '1'));
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begin
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-- Check each pattern.
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for i in patterns'range loop
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-- Set the inputs.
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cin <= patterns(i).cin;
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sel <= patterns(i).sel;
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-- Wait for the results.
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wait for 1 ns;
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-- Check the outputs.
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assert a = patterns(i).a
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report "bad dmux4way" severity error;
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assert b = patterns(i).b
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report "bad dmux4way" severity error;
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assert c = patterns(i).c
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report "bad dmux4way" severity error;
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assert d = patterns(i).d
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report "bad dmux4way" severity error;
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end loop;
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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end process;
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end dmux4way_tb_arch;
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