24 lines
761 B
VHDL
24 lines
761 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity dmux8way is
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port (cin : in std_logic;
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sel : in std_logic_vector(2 downto 0);
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a, b, c, d, e, f, g, h : out std_logic);
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end dmux8way;
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architecture dmux8way_arch of dmux8way is
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component dmux
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port (cin, sel : in std_logic; a, b : out std_logic);
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end component;
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component dmux4way
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port (cin : in std_logic; sel : in std_logic_vector(1 downto 0); a, b, c, d : out std_logic);
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end component;
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signal dm0, dm1 : std_logic;
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begin
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dmux_0: dmux port map (cin, sel(2), dm0, dm1);
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dmux4way_0: dmux4way port map (dm0, sel(1 downto 0), a, b, c, d);
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dmux4way_1: dmux4way port map (dm1, sel(1 downto 0), e, f, g, h);
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end dmux8way_arch;
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