19 lines
493 B
VHDL
19 lines
493 B
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity dregister is
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port (d : in std_logic_vector(15 downto 0);
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load, clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end dregister;
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architecture dregister_arch of dregister is
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component dbit
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port (d, load, clk : in std_logic; cout : out std_logic);
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end component;
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begin
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reg: for i in 0 to 15 generate
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dbit_i: dbit port map (d(i), load, clk, cout(i));
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end generate;
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end dregister_arch;
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