63 lines
2.7 KiB
VHDL
63 lines
2.7 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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-- A testbench has no ports.
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entity mux4way16_tb is
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end mux4way16_tb;
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architecture mux4way16_tb_arch of mux4way16_tb is
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-- Declaration of the component that will be instantiated.
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component mux4way16
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port (a, b, c, d : in std_logic_vector(15 downto 0);
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sel : in std_logic_vector(1 downto 0);
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cout : out std_logic_vector(15 downto 0));
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end component;
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-- Specifies which entity is bound with the component.
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for mux4way16_0: mux4way16 use entity work.mux4way16;
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signal a, b, c, d, cout : std_logic_vector(15 downto 0);
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signal sel : std_logic_vector(1 downto 0);
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begin
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-- Component instantiation.
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mux4way16_0: mux4way16 port map (a, b, c, d, sel, cout);
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-- This process does the real job.
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process
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type pattern_type is record
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-- The inputs of the mux4way16.
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a, b, c, d : std_logic_vector(15 downto 0);
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sel : std_logic_vector(1 downto 0);
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-- The expected outputs of the mux4way16.
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cout : std_logic_vector(15 downto 0);
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end record;
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-- The patterns to apply.
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type pattern_array is array (natural range <>) of pattern_type;
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constant patterns : pattern_array :=
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(("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "00", "0000000000000000"),
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("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "01", "0000000000000000"),
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("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "10", "0000000000000000"),
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("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "11", "0000000000000000"),
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("0001001000110100", "1001100001110110", "1010101010101010", "0101010101010101", "00", "0001001000110100"),
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("0001001000110100", "1001100001110110", "1010101010101010", "0101010101010101", "01", "1001100001110110"),
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("0001001000110100", "1001100001110110", "1010101010101010", "0101010101010101", "10", "1010101010101010"),
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("0001001000110100", "1001100001110110", "1010101010101010", "0101010101010101", "11", "0101010101010101"));
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begin
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-- Check each pattern.
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for i in patterns'range loop
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-- Set the inputs.
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a <= patterns(i).a;
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b <= patterns(i).b;
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c <= patterns(i).c;
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d <= patterns(i).d;
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sel <= patterns(i).sel;
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-- Wait for the results.
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wait for 1 ns;
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-- Check the outputs.
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assert cout = patterns(i).cout
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report "bad mux4way16 output" severity error;
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end loop;
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assert false report "end of test" severity note;
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-- Wait forever; this will finish the simulation.
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wait;
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end process;
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end mux4way16_tb_arch;
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