47 lines
1.7 KiB
VHDL
47 lines
1.7 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity pc is
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port (d : in std_logic_vector(15 downto 0);
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load, inc, reset, clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end pc;
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architecture pc_arch of pc is
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component dregister
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port (d : in std_logic_vector(15 downto 0);
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load, clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end component;
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component mux8way16
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port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
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sel : in std_logic_vector(2 downto 0);
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cout : out std_logic_vector(15 downto 0));
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end component;
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component add16
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port (a, b : std_logic_vector(15 downto 0); cout : out std_logic_vector(15 downto 0));
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end component;
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signal regLoad : std_logic;
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signal regOut, regOutInc, coutT : std_logic_vector(15 downto 0);
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signal muxsel : std_logic_vector(2 downto 0);
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constant zeroes : std_logic_vector(15 downto 0) := "0000000000000000";
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begin
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muxsel <= reset & load & inc;
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regLoad <= load or inc or reset;
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add16_0: add16 port map ("0000000000000001", regOut, regOutInc);
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-- regOutInc <= std_logic_vector(unsigned(regOut) + 1);
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--coutT <= "0000000000000000" when (reset = '1') else
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-- d when (load = '1') else
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-- regOutInc when (inc = '1') else
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-- regOut;
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mux8way16_0: mux8way16 port map (regOut, regOutInc, d, d, zeroes, zeroes, zeroes, zeroes, muxsel, coutT);
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reg_0: dregister port map (coutT, regLoad, clk, regOut);
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cout <= regOut;
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end pc_arch;
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