41 lines
1.6 KiB
VHDL
41 lines
1.6 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity ram16k is
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port (d : in std_logic_vector(15 downto 0);
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load : in std_logic;
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address : in std_logic_vector(14 downto 0);
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clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end ram16k;
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architecture ram16k_arch of ram16k is
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component ram4k
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port (d : in std_logic_vector(15 downto 0);
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load : in std_logic;
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address : in std_logic_vector(11 downto 0);
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clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end component;
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component dmux8way
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port (cin : in std_logic; sel : in std_logic_vector(2 downto 0); a, b, c, d, e, f, g, h : out std_logic);
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end component;
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component mux8way16
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port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
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sel : in std_logic_vector(2 downto 0);
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cout : out std_logic_vector(15 downto 0));
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end component;
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signal ramLoad : std_logic_vector(7 downto 0);
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type ramoutT is array (7 downto 0) of std_logic_vector(15 downto 0);
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signal ramOut : ramoutT;
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begin
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dmux8way_0: dmux8way port map (load, address(2 downto 0), ramLoad(0), ramLoad(1), ramLoad(2), ramLoad(3), ramLoad(4), ramLoad(5), ramLoad(6), ramLoad(7));
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ram: for i in ramLoad'range generate
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ram4k_i: ram4k port map (d, ramLoad(i), address(14 downto 3), clk, ramOut(i));
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end generate;
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mux8way16_0: mux8way16 port map (ramOut(0), ramOut(1), ramOut(2), ramOut(3), ramOut(4), ramOut(5), ramOut(6), ramOut(7), address(2 downto 0), cout);
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end ram16k_arch;
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