39 lines
1.5 KiB
VHDL
39 lines
1.5 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity ram8 is
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port (d : in std_logic_vector(15 downto 0);
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load : in std_logic;
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address : in std_logic_vector(2 downto 0);
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clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end ram8;
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architecture ram8_arch of ram8 is
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component dregister
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port (d : in std_logic_vector(15 downto 0);
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load, clk : in std_logic;
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cout : out std_logic_vector(15 downto 0));
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end component;
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component dmux8way
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port (cin : in std_logic; sel : in std_logic_vector(2 downto 0); a, b, c, d, e, f, g, h : out std_logic);
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end component;
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component mux8way16
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port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
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sel : in std_logic_vector(2 downto 0);
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cout : out std_logic_vector(15 downto 0));
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end component;
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signal regLoad : std_logic_vector(7 downto 0);
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type regoutT is array (7 downto 0) of std_logic_vector(15 downto 0);
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signal regOut : regoutT;
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begin
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dmux8way_0: dmux8way port map (load, address, regLoad(0), regLoad(1), regLoad(2), regLoad(3), regLoad(4), regLoad(5), regLoad(6), regLoad(7));
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reg: for i in regLoad'range generate
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dregister_i: dregister port map (d, regLoad(i), clk, regOut(i));
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end generate;
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mux8way16_0: mux8way16 port map (regOut(0), regOut(1), regOut(2), regOut(3), regOut(4), regOut(5), regOut(6), regOut(7), address, cout);
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end ram8_arch;
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