An implementation of the Hack computer in VHDL based off of the Nand to Tetris course.

Collin J. Doering b38cec30f0 Initial implementation of hack cpu and test bench ... The test bench 'cpu_tb.vhdl' currently fails for almost all inputs. Though from analysis of the vcd output, everything seems to be working correctly. It seems that the compare data from the nand to tetris course for synchronized circuits/chips does not behave nicely with this simulation because it assumes two clock cycles is one discreet time unit (tick-tock) whereas in this simulation every pulse of the clock (1 ns period) acts as a single discreet time unit. This however still needs to be investigated and also is an issue in the implementation of 'pc_tb.vhdl'. Signed-off-by: Collin J. Doering <collin.doering@rekahsoft.ca>		2015-05-23 03:39:37 -04:00
schematics	Initial commit	2015-05-21 15:12:01 -04:00
src	Initial implementation of hack cpu and test bench	2015-05-23 03:39:37 -04:00
.gitignore	Fix gitignore files	2015-05-21 19:11:38 -04:00
gpl.txt	Added GPL3 license and cleaned up formatting	2015-05-22 02:14:14 -04:00