Collin J. Doering
6ab2badb26
Contains vhdl code and test benches for the following chips: - adder - add16 - alu - dff - dbit - dregister - dmux - dmux4way - dmux8way - mux - mux16 - mux4way16 - mux8way16 - pc - ram8 - ram64 - ram512 - ram4k - ram16k For simulation of sequential chips, a clock must be used; this is implemented as 'src/clock.vhdl' with accompanying test bench 'src/clock_tb.vhdl'. 'src/wave/gktw' contains gtkwave save files for viewing the output of the various test benches. The 'schematics' directory contains schematics of the various chips (incomplete). Things not yet completed: - weird issue with 'src/pc_tb.vhdl'; that is, the test data from the "nand to tetris" course doesn't fit the simulation but the simulation appears to be correct (by inspection). - cpu chip - build system (currently things can built by hand using ghdl as follows) To build the various chips and their respective test benches, use ghdl like so: $ cd src $ ghdl -i --workdir=work *.vhdl $ ghdl -m --workdir=work <chip_name>_tb $ ghdl -r <chip_name>_tb --vcd=wave/vcd/<chip_name>.vcd You can then view the wave output file in 'src/wave/vcd/<chip_name>.vcd'.
105 lines
2.1 KiB
Plaintext
105 lines
2.1 KiB
Plaintext
v 20130925 2
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C 40000 40000 0 0 0 title-B.sym
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C 48100 45300 1 0 0 EMBEDDED7400-1.sym
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[
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L 48400 45500 48400 46100 3 0 0 0 -1 -1
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L 48400 46100 48800 46100 3 0 0 0 -1 -1
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L 48400 45500 48800 45500 3 0 0 0 -1 -1
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A 48800 45800 300 270 180 3 0 0 0 -1 -1
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V 49150 45800 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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P 49200 45800 49400 45800 1 0 1
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{
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pinlabel=Y
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T 48300 46050 5 8 1 1 0 6 1
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}
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T 48400 45300 9 8 1 0 0 0 1
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7400
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T 48600 46200 5 10 0 0 0 0 1
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device=7400
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T 48600 46400 5 10 0 0 0 0 1
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slot=1
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T 48600 46600 5 10 0 0 0 0 1
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numslots=4
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T 48600 46800 5 10 0 0 0 0 1
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slotdef=1:1,2,3
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T 48600 47000 5 10 0 0 0 0 1
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slotdef=2:4,5,6
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T 48600 47200 5 10 0 0 0 0 1
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slotdef=3:9,10,8
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T 48600 47400 5 10 0 0 0 0 1
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slotdef=4:12,13,11
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T 48400 46200 8 10 0 1 0 0 1
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refdes=U?
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T 48600 47550 5 10 0 0 0 0 1
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footprint=DIP14
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T 48600 47750 5 10 0 0 0 0 1
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description=4 NAND gates with 2 inputs
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T 48600 48150 5 10 0 0 0 0 1
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net=Vcc:14
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T 48600 48350 5 10 0 0 0 0 1
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net=GND:7
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T 48600 47950 5 10 0 0 0 0 1
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documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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]
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{
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T 48600 46200 5 10 0 0 0 0 1
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device=7400
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T 48600 47550 5 10 0 0 0 0 1
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footprint=DIP14
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T 48400 46200 5 10 1 1 0 0 1
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refdes=U1
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}
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N 48100 45600 48100 46000 4
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P 48100 45800 47700 45800 1 0 0
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{
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T 47695 45845 5 10 1 1 0 0 1
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pinnumber=0
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}
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T 50100 40700 9 10 1 0 0 0 1
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Not gate constructed from nand gate
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P 49400 45800 49700 45800 1 0 0
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