Initial commit
Contains vhdl code and test benches for the following chips: - adder - add16 - alu - dff - dbit - dregister - dmux - dmux4way - dmux8way - mux - mux16 - mux4way16 - mux8way16 - pc - ram8 - ram64 - ram512 - ram4k - ram16k For simulation of sequential chips, a clock must be used; this is implemented as 'src/clock.vhdl' with accompanying test bench 'src/clock_tb.vhdl'. 'src/wave/gktw' contains gtkwave save files for viewing the output of the various test benches. The 'schematics' directory contains schematics of the various chips (incomplete). Things not yet completed: - weird issue with 'src/pc_tb.vhdl'; that is, the test data from the "nand to tetris" course doesn't fit the simulation but the simulation appears to be correct (by inspection). - cpu chip - build system (currently things can built by hand using ghdl as follows) To build the various chips and their respective test benches, use ghdl like so: $ cd src $ ghdl -i --workdir=work *.vhdl $ ghdl -m --workdir=work <chip_name>_tb $ ghdl -r <chip_name>_tb --vcd=wave/vcd/<chip_name>.vcd You can then view the wave output file in 'src/wave/vcd/<chip_name>.vcd'.
This commit is contained in:
commit
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*~
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src/work-obj93.cf
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schematics/and.sch
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v 20130925 2
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net=GND:7
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documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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]
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T 49000 48050 5 10 0 0 0 0 1
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net=Vcc:14
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T 49000 48250 5 10 0 0 0 0 1
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net=GND:7
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T 49000 47850 5 10 0 0 0 0 1
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documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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]
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{
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N 48200 45700 48500 45700 4
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T 50100 40700 9 10 1 0 0 0 1
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And gate contructed from nand gates
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P 46900 45900 46700 45900 1 0 0
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C 40000 40000 0 0 0 title-B.sym
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[
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L 48400 45500 48400 46100 3 0 0 0 -1 -1
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L 48400 46100 48800 46100 3 0 0 0 -1 -1
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L 48400 45500 48800 45500 3 0 0 0 -1 -1
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A 48800 45800 300 270 180 3 0 0 0 -1 -1
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P 49200 45800 49400 45800 1 0 1
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{
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{
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7400
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device=7400
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T 48600 46600 5 10 0 0 0 0 1
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T 48600 46800 5 10 0 0 0 0 1
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slotdef=1:1,2,3
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T 48600 47000 5 10 0 0 0 0 1
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T 48600 47200 5 10 0 0 0 0 1
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slotdef=3:9,10,8
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slotdef=4:12,13,11
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T 48400 46200 8 10 0 1 0 0 1
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refdes=U?
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T 48600 47550 5 10 0 0 0 0 1
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footprint=DIP14
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T 48600 47750 5 10 0 0 0 0 1
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description=4 NAND gates with 2 inputs
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T 48600 48150 5 10 0 0 0 0 1
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net=Vcc:14
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||||||
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T 48600 48350 5 10 0 0 0 0 1
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net=GND:7
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T 48600 47950 5 10 0 0 0 0 1
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documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
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]
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{
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T 48600 46200 5 10 0 0 0 0 1
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T 48600 47550 5 10 0 0 0 0 1
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||||||
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T 48400 46200 5 10 1 1 0 0 1
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||||||
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refdes=U1
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||||||
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}
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||||||
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N 48100 45600 48100 46000 4
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P 48100 45800 47700 45800 1 0 0
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{
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T 48100 45800 5 10 0 0 0 0 1
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pinnumber=0
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}
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T 50100 40700 9 10 1 0 0 0 1
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Not gate constructed from nand gate
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P 49400 45800 49700 45800 1 0 0
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{
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||||||
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T 49755 45795 5 10 1 1 0 0 1
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pinlabel=cout
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T 49705 45845 5 10 1 1 0 6 1
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pinnumber=0
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T 49400 45800 5 10 0 0 0 0 1
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||||||
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pinseq=0
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||||||
|
}
|
272
schematics/or.sch
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schematics/or.sch
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v 20130925 2
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C 40000 40000 0 0 0 title-B.sym
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C 47300 45600 1 0 0 EMBEDDED7400-1.sym
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[
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L 47600 45800 47600 46400 3 0 0 0 -1 -1
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||||||
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L 47600 46400 48000 46400 3 0 0 0 -1 -1
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L 47600 45800 48000 45800 3 0 0 0 -1 -1
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||||||
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A 48000 46100 300 270 180 3 0 0 0 -1 -1
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V 48350 46100 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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P 48400 46100 48600 46100 1 0 1
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||||||
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{
|
||||||
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T 48400 46150 5 8 1 1 0 0 1
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||||||
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pinnumber=3
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||||||
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T 48400 46050 5 8 0 1 0 2 1
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||||||
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pinseq=3
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||||||
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T 48250 46100 9 8 0 1 0 6 1
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pinlabel=Y
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T 48250 46100 5 8 0 1 0 8 1
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pintype=out
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||||||
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}
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||||||
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P 47600 45900 47300 45900 1 0 1
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||||||
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{
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||||||
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T 47500 45950 5 8 1 1 0 6 1
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pinnumber=2
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T 47500 45850 5 8 0 1 0 8 1
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pinseq=2
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T 47650 45900 9 8 0 1 0 0 1
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pinlabel=B
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||||||
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T 47650 45900 5 8 0 1 0 2 1
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||||||
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pintype=in
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||||||
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}
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||||||
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P 47600 46300 47300 46300 1 0 1
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||||||
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{
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||||||
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T 47500 46350 5 8 1 1 0 6 1
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pinnumber=1
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T 47500 46250 5 8 0 1 0 8 1
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pinseq=1
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T 47650 46300 9 8 0 1 0 0 1
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pinlabel=A
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T 47650 46300 5 8 0 1 0 2 1
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||||||
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pintype=in
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}
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T 47600 45600 9 8 1 0 0 0 1
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7400
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T 47800 46500 5 10 0 0 0 0 1
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device=7400
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T 47800 46700 5 10 0 0 0 0 1
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slot=1
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T 47800 46900 5 10 0 0 0 0 1
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numslots=4
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T 47800 47100 5 10 0 0 0 0 1
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slotdef=1:1,2,3
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T 47800 47300 5 10 0 0 0 0 1
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slotdef=2:4,5,6
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T 47800 47500 5 10 0 0 0 0 1
|
||||||
|
slotdef=3:9,10,8
|
||||||
|
T 47800 47700 5 10 0 0 0 0 1
|
||||||
|
slotdef=4:12,13,11
|
||||||
|
T 47600 46500 8 10 0 1 0 0 1
|
||||||
|
refdes=U?
|
||||||
|
T 47800 47850 5 10 0 0 0 0 1
|
||||||
|
footprint=DIP14
|
||||||
|
T 47800 48050 5 10 0 0 0 0 1
|
||||||
|
description=4 NAND gates with 2 inputs
|
||||||
|
T 47800 48450 5 10 0 0 0 0 1
|
||||||
|
net=Vcc:14
|
||||||
|
T 47800 48650 5 10 0 0 0 0 1
|
||||||
|
net=GND:7
|
||||||
|
T 47800 48250 5 10 0 0 0 0 1
|
||||||
|
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
|
||||||
|
]
|
||||||
|
{
|
||||||
|
T 47800 46500 5 10 0 0 0 0 1
|
||||||
|
device=7400
|
||||||
|
T 47800 47850 5 10 0 0 0 0 1
|
||||||
|
footprint=DIP14
|
||||||
|
T 47600 46500 5 10 1 1 0 0 1
|
||||||
|
refdes=U1
|
||||||
|
}
|
||||||
|
C 47300 44500 1 0 0 EMBEDDED7400-1.sym
|
||||||
|
[
|
||||||
|
L 47600 44700 47600 45300 3 0 0 0 -1 -1
|
||||||
|
L 47600 45300 48000 45300 3 0 0 0 -1 -1
|
||||||
|
L 47600 44700 48000 44700 3 0 0 0 -1 -1
|
||||||
|
A 48000 45000 300 270 180 3 0 0 0 -1 -1
|
||||||
|
V 48350 45000 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
||||||
|
P 48400 45000 48600 45000 1 0 1
|
||||||
|
{
|
||||||
|
T 48400 45050 5 8 1 1 0 0 1
|
||||||
|
pinnumber=3
|
||||||
|
T 48400 44950 5 8 0 1 0 2 1
|
||||||
|
pinseq=3
|
||||||
|
T 48250 45000 9 8 0 1 0 6 1
|
||||||
|
pinlabel=Y
|
||||||
|
T 48250 45000 5 8 0 1 0 8 1
|
||||||
|
pintype=out
|
||||||
|
}
|
||||||
|
P 47600 44800 47300 44800 1 0 1
|
||||||
|
{
|
||||||
|
T 47500 44850 5 8 1 1 0 6 1
|
||||||
|
pinnumber=2
|
||||||
|
T 47500 44750 5 8 0 1 0 8 1
|
||||||
|
pinseq=2
|
||||||
|
T 47650 44800 9 8 0 1 0 0 1
|
||||||
|
pinlabel=B
|
||||||
|
T 47650 44800 5 8 0 1 0 2 1
|
||||||
|
pintype=in
|
||||||
|
}
|
||||||
|
P 47600 45200 47300 45200 1 0 1
|
||||||
|
{
|
||||||
|
T 47500 45250 5 8 1 1 0 6 1
|
||||||
|
pinnumber=1
|
||||||
|
T 47500 45150 5 8 0 1 0 8 1
|
||||||
|
pinseq=1
|
||||||
|
T 47650 45200 9 8 0 1 0 0 1
|
||||||
|
pinlabel=A
|
||||||
|
T 47650 45200 5 8 0 1 0 2 1
|
||||||
|
pintype=in
|
||||||
|
}
|
||||||
|
T 47600 44500 9 8 1 0 0 0 1
|
||||||
|
7400
|
||||||
|
T 47800 45400 5 10 0 0 0 0 1
|
||||||
|
device=7400
|
||||||
|
T 47800 45600 5 10 0 0 0 0 1
|
||||||
|
slot=1
|
||||||
|
T 47800 45800 5 10 0 0 0 0 1
|
||||||
|
numslots=4
|
||||||
|
T 47800 46000 5 10 0 0 0 0 1
|
||||||
|
slotdef=1:1,2,3
|
||||||
|
T 47800 46200 5 10 0 0 0 0 1
|
||||||
|
slotdef=2:4,5,6
|
||||||
|
T 47800 46400 5 10 0 0 0 0 1
|
||||||
|
slotdef=3:9,10,8
|
||||||
|
T 47800 46600 5 10 0 0 0 0 1
|
||||||
|
slotdef=4:12,13,11
|
||||||
|
T 47600 45400 8 10 0 1 0 0 1
|
||||||
|
refdes=U?
|
||||||
|
T 47800 46750 5 10 0 0 0 0 1
|
||||||
|
footprint=DIP14
|
||||||
|
T 47800 46950 5 10 0 0 0 0 1
|
||||||
|
description=4 NAND gates with 2 inputs
|
||||||
|
T 47800 47350 5 10 0 0 0 0 1
|
||||||
|
net=Vcc:14
|
||||||
|
T 47800 47550 5 10 0 0 0 0 1
|
||||||
|
net=GND:7
|
||||||
|
T 47800 47150 5 10 0 0 0 0 1
|
||||||
|
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
|
||||||
|
]
|
||||||
|
{
|
||||||
|
T 47800 45400 5 10 0 0 0 0 1
|
||||||
|
device=7400
|
||||||
|
T 47800 46750 5 10 0 0 0 0 1
|
||||||
|
footprint=DIP14
|
||||||
|
T 47600 45400 5 10 1 1 0 0 1
|
||||||
|
refdes=U2
|
||||||
|
}
|
||||||
|
C 48600 45100 1 0 0 EMBEDDED7400-1.sym
|
||||||
|
[
|
||||||
|
L 48900 45300 48900 45900 3 0 0 0 -1 -1
|
||||||
|
L 48900 45900 49300 45900 3 0 0 0 -1 -1
|
||||||
|
L 48900 45300 49300 45300 3 0 0 0 -1 -1
|
||||||
|
A 49300 45600 300 270 180 3 0 0 0 -1 -1
|
||||||
|
V 49650 45600 50 6 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
|
||||||
|
P 49700 45600 49900 45600 1 0 1
|
||||||
|
{
|
||||||
|
T 49700 45650 5 8 1 1 0 0 1
|
||||||
|
pinnumber=3
|
||||||
|
T 49700 45550 5 8 0 1 0 2 1
|
||||||
|
pinseq=3
|
||||||
|
T 49550 45600 9 8 0 1 0 6 1
|
||||||
|
pinlabel=Y
|
||||||
|
T 49550 45600 5 8 0 1 0 8 1
|
||||||
|
pintype=out
|
||||||
|
}
|
||||||
|
P 48900 45400 48600 45400 1 0 1
|
||||||
|
{
|
||||||
|
T 48800 45450 5 8 1 1 0 6 1
|
||||||
|
pinnumber=2
|
||||||
|
T 48800 45350 5 8 0 1 0 8 1
|
||||||
|
pinseq=2
|
||||||
|
T 48950 45400 9 8 0 1 0 0 1
|
||||||
|
pinlabel=B
|
||||||
|
T 48950 45400 5 8 0 1 0 2 1
|
||||||
|
pintype=in
|
||||||
|
}
|
||||||
|
P 48900 45800 48600 45800 1 0 1
|
||||||
|
{
|
||||||
|
T 48800 45850 5 8 1 1 0 6 1
|
||||||
|
pinnumber=1
|
||||||
|
T 48800 45750 5 8 0 1 0 8 1
|
||||||
|
pinseq=1
|
||||||
|
T 48950 45800 9 8 0 1 0 0 1
|
||||||
|
pinlabel=A
|
||||||
|
T 48950 45800 5 8 0 1 0 2 1
|
||||||
|
pintype=in
|
||||||
|
}
|
||||||
|
T 48900 45100 9 8 1 0 0 0 1
|
||||||
|
7400
|
||||||
|
T 49100 46000 5 10 0 0 0 0 1
|
||||||
|
device=7400
|
||||||
|
T 49100 46200 5 10 0 0 0 0 1
|
||||||
|
slot=1
|
||||||
|
T 49100 46400 5 10 0 0 0 0 1
|
||||||
|
numslots=4
|
||||||
|
T 49100 46600 5 10 0 0 0 0 1
|
||||||
|
slotdef=1:1,2,3
|
||||||
|
T 49100 46800 5 10 0 0 0 0 1
|
||||||
|
slotdef=2:4,5,6
|
||||||
|
T 49100 47000 5 10 0 0 0 0 1
|
||||||
|
slotdef=3:9,10,8
|
||||||
|
T 49100 47200 5 10 0 0 0 0 1
|
||||||
|
slotdef=4:12,13,11
|
||||||
|
T 48900 46000 8 10 0 1 0 0 1
|
||||||
|
refdes=U?
|
||||||
|
T 49100 47350 5 10 0 0 0 0 1
|
||||||
|
footprint=DIP14
|
||||||
|
T 49100 47550 5 10 0 0 0 0 1
|
||||||
|
description=4 NAND gates with 2 inputs
|
||||||
|
T 49100 47950 5 10 0 0 0 0 1
|
||||||
|
net=Vcc:14
|
||||||
|
T 49100 48150 5 10 0 0 0 0 1
|
||||||
|
net=GND:7
|
||||||
|
T 49100 47750 5 10 0 0 0 0 1
|
||||||
|
documentation=http://www-s.ti.com/sc/ds/sn74hc00.pdf
|
||||||
|
]
|
||||||
|
{
|
||||||
|
T 49100 46000 5 10 0 0 0 0 1
|
||||||
|
device=7400
|
||||||
|
T 49100 47350 5 10 0 0 0 0 1
|
||||||
|
footprint=DIP14
|
||||||
|
T 48900 46000 5 10 1 1 0 0 1
|
||||||
|
refdes=U3
|
||||||
|
}
|
||||||
|
N 47300 45900 47300 46300 4
|
||||||
|
N 47300 44800 47300 45200 4
|
||||||
|
N 48600 45000 48600 45400 4
|
||||||
|
N 48600 46100 48600 45800 4
|
||||||
|
T 50100 40700 9 10 1 0 0 0 1
|
||||||
|
Or Gate Contructed from Nand Gates
|
||||||
|
P 49900 45600 50200 45600 1 0 0
|
||||||
|
{
|
||||||
|
T 49900 45600 5 10 0 0 0 0 1
|
||||||
|
pintype=unknown
|
||||||
|
T 50255 45595 5 10 1 1 0 0 1
|
||||||
|
pinlabel=cout
|
||||||
|
T 50105 45645 5 10 0 1 0 6 1
|
||||||
|
pinnumber=0
|
||||||
|
T 49900 45600 5 10 0 0 0 0 1
|
||||||
|
pinseq=0
|
||||||
|
}
|
||||||
|
P 47300 46100 47000 46100 1 0 0
|
||||||
|
{
|
||||||
|
T 47300 46100 5 10 0 0 0 0 1
|
||||||
|
pintype=unknown
|
||||||
|
T 46945 46095 5 10 1 1 0 6 1
|
||||||
|
pinlabel=a
|
||||||
|
T 47095 46145 5 10 0 1 0 0 1
|
||||||
|
pinnumber=0
|
||||||
|
T 47300 46100 5 10 0 0 0 0 1
|
||||||
|
pinseq=0
|
||||||
|
}
|
||||||
|
P 47300 45000 47000 45000 1 0 0
|
||||||
|
{
|
||||||
|
T 47300 45000 5 10 0 0 0 0 1
|
||||||
|
pintype=unknown
|
||||||
|
T 46945 44995 5 10 1 1 0 6 1
|
||||||
|
pinlabel=b
|
||||||
|
T 47095 45045 5 10 1 1 0 0 1
|
||||||
|
pinnumber=0
|
||||||
|
T 47300 45000 5 10 0 0 0 0 1
|
||||||
|
pinseq=0
|
||||||
|
}
|
19
src/DFF.vhdl
Normal file
19
src/DFF.vhdl
Normal file
@ -0,0 +1,19 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity DFF is
|
||||||
|
port (d, clk : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end DFF;
|
||||||
|
|
||||||
|
architecture DFF_arch of DFF is
|
||||||
|
signal coutFst : std_logic := '0';
|
||||||
|
begin
|
||||||
|
cout <= coutFst;
|
||||||
|
dff: process(clk)
|
||||||
|
begin
|
||||||
|
if (rising_edge(clk)) then
|
||||||
|
coutFst <= d;
|
||||||
|
end if;
|
||||||
|
end process dff;
|
||||||
|
end DFF_arch;
|
63
src/DFF_tb.vhdl
Normal file
63
src/DFF_tb.vhdl
Normal file
@ -0,0 +1,63 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity DFF_tb is
|
||||||
|
end DFF_tb;
|
||||||
|
|
||||||
|
architecture DFF_tb_arch of DFF_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component DFF
|
||||||
|
port (d, clk : in std_logic; cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
-- Declaration of the clock
|
||||||
|
component Clock
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for DFF_0: DFF use entity work.DFF;
|
||||||
|
signal d, finish, clk, cout : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
OSC_CLK: Clock port map (finish, clk);
|
||||||
|
DFF_0: DFF port map (d, clk, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the DFF.
|
||||||
|
d : std_logic;
|
||||||
|
-- The output of the DFF.
|
||||||
|
cout : std_logic;
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(('0', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '1'),
|
||||||
|
('0', '1'),
|
||||||
|
('0', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('0', '1'));
|
||||||
|
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
d <= patterns(i).d;
|
||||||
|
wait for 0.25 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad data; nothing remembered" severity error;
|
||||||
|
wait for 0.75 ns;
|
||||||
|
end loop;
|
||||||
|
-- End the clock
|
||||||
|
finish <= '1';
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end DFF_tb_arch;
|
31
src/add16.vhdl
Normal file
31
src/add16.vhdl
Normal file
@ -0,0 +1,31 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity add16 is
|
||||||
|
port (a, b : in std_logic_vector(15 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end add16;
|
||||||
|
|
||||||
|
architecture add16_arch of add16 is
|
||||||
|
component adder
|
||||||
|
port (a, b, ci : in std_logic; s, co : out std_logic);
|
||||||
|
end component;
|
||||||
|
signal co0, co1, co2, co3, co4, co5, co6, co7, co8, co9, co10, co11, co12, co13, co14 : std_logic;
|
||||||
|
begin
|
||||||
|
adder_0: adder port map (a(0), b(0), '0', cout(0), co0);
|
||||||
|
adder_1: adder port map (a(1), b(1), co0, cout(1), co1);
|
||||||
|
adder_2: adder port map (a(2), b(2), co1, cout(2), co2);
|
||||||
|
adder_3: adder port map (a(3), b(3), co2, cout(3), co3);
|
||||||
|
adder_4: adder port map (a(4), b(4), co3, cout(4), co4);
|
||||||
|
adder_5: adder port map (a(5), b(5), co4, cout(5), co5);
|
||||||
|
adder_6: adder port map (a(6), b(6), co5, cout(6), co6);
|
||||||
|
adder_7: adder port map (a(7), b(7), co6, cout(7), co7);
|
||||||
|
adder_8: adder port map (a(8), b(8), co7, cout(8), co8);
|
||||||
|
adder_9: adder port map (a(9), b(9), co8, cout(9), co9);
|
||||||
|
adder_10: adder port map (a(10), b(10), co9, cout(10), co10);
|
||||||
|
adder_11: adder port map (a(11), b(11), co10, cout(11), co11);
|
||||||
|
adder_12: adder port map (a(12), b(12), co11, cout(12), co12);
|
||||||
|
adder_13: adder port map (a(13), b(13), co12, cout(13), co13);
|
||||||
|
adder_14: adder port map (a(14), b(14), co13, cout(14), co14);
|
||||||
|
adder_15: adder port map (a(15), b(15), co14, cout(15), open);
|
||||||
|
end add16_arch;
|
64
src/add16_tb.vhdl
Normal file
64
src/add16_tb.vhdl
Normal file
@ -0,0 +1,64 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity add16_tb is
|
||||||
|
end add16_tb;
|
||||||
|
|
||||||
|
architecture add16_tb_arch of add16_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component add16
|
||||||
|
port (a, b : std_logic_vector(15 downto 0); cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for add16_0: add16 use entity work.add16;
|
||||||
|
signal a, b, cout : std_logic_vector(15 downto 0);
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
add16_0: add16 port map (a, b, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the add16.
|
||||||
|
a, b : std_logic_vector(15 downto 0);
|
||||||
|
-- The expected output of the add16.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", "0000000000000000", "0000000000000000"),
|
||||||
|
("0000000000000001", "0000000000000000", "0000000000000001"),
|
||||||
|
("0000000000000001", "0000000000000001", "0000000000000010"),
|
||||||
|
("0000000000000010", "0000000000000001", "0000000000000011"),
|
||||||
|
("0000000000000011", "0000000000000001", "0000000000000100"),
|
||||||
|
("0000000000000010", "0000000000000100", "0000000000000110"),
|
||||||
|
("1000000000000000", "1000000000000000", "0000000000000000"),
|
||||||
|
("1100000000000011", "1100000000000111", "1000000000001010"),
|
||||||
|
|
||||||
|
-- Tests given by Nand to tetris course
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000"),
|
||||||
|
("0000000000000000", "1111111111111111", "1111111111111111"),
|
||||||
|
("1111111111111111", "1111111111111111", "1111111111111110"),
|
||||||
|
("1010101010101010", "0101010101010101", "1111111111111111"),
|
||||||
|
("0011110011000011", "0000111111110000", "0100110010110011"),
|
||||||
|
("0001001000110100", "1001100001110110", "1010101010101010"));
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
a <= patterns(i).a;
|
||||||
|
b <= patterns(i).b;
|
||||||
|
cout <= patterns(i).cout;
|
||||||
|
-- Wait for the results.
|
||||||
|
wait for 1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "incorrect addition" severity error;
|
||||||
|
end loop;
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end add16_tb_arch;
|
17
src/adder.vhdl
Normal file
17
src/adder.vhdl
Normal file
@ -0,0 +1,17 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity adder is
|
||||||
|
-- i0, i1 and the carry-in ci are inputs of the adder.
|
||||||
|
-- s is the sum output, co is the carry-out.
|
||||||
|
port (a, b, ci : in std_logic;
|
||||||
|
s, co : out std_logic);
|
||||||
|
end adder;
|
||||||
|
|
||||||
|
architecture adder_arch of adder is
|
||||||
|
begin
|
||||||
|
-- Compute the sum.
|
||||||
|
s <= a xor b xor ci;
|
||||||
|
-- Compute the carry.
|
||||||
|
co <= (a and b) or (a and ci) or (b and ci);
|
||||||
|
end adder_arch;
|
58
src/adder_tb.vhdl
Normal file
58
src/adder_tb.vhdl
Normal file
@ -0,0 +1,58 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity adder_tb is
|
||||||
|
end adder_tb;
|
||||||
|
|
||||||
|
architecture adder_tb_arch of adder_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component adder
|
||||||
|
port (a, b, ci : in std_logic; s, co : out std_logic);
|
||||||
|
end component;
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for adder_0: adder use entity work.adder;
|
||||||
|
signal a, b, ci, s, co : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
adder_0: adder port map (a, b, ci, s, co);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the adder.
|
||||||
|
a, b, ci : std_logic;
|
||||||
|
-- The expected outputs of the adder.
|
||||||
|
s, co : std_logic;
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(('0', '0', '0', '0', '0'),
|
||||||
|
('0', '0', '1', '1', '0'),
|
||||||
|
('0', '1', '0', '1', '0'),
|
||||||
|
('0', '1', '1', '0', '1'),
|
||||||
|
('1', '0', '0', '1', '0'),
|
||||||
|
('1', '0', '1', '0', '1'),
|
||||||
|
('1', '1', '0', '0', '1'),
|
||||||
|
('1', '1', '1', '1', '1'));
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
a <= patterns(i).a;
|
||||||
|
b <= patterns(i).b;
|
||||||
|
ci <= patterns(i).ci;
|
||||||
|
-- Wait for the results.
|
||||||
|
wait for 1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert s = patterns(i).s
|
||||||
|
report "bad sum value" severity error;
|
||||||
|
assert co = patterns(i).co
|
||||||
|
report "bad carray out value" severity error;
|
||||||
|
end loop;
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end adder_tb_arch;
|
40
src/alu.vhdl
Normal file
40
src/alu.vhdl
Normal file
@ -0,0 +1,40 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity alu is
|
||||||
|
port (x, y : in std_logic_vector(15 downto 0);
|
||||||
|
zx, nx, zy, ny, f, no : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0);
|
||||||
|
zr, ng : out std_logic);
|
||||||
|
end alu;
|
||||||
|
|
||||||
|
architecture alu_arch of alu is
|
||||||
|
component mux16
|
||||||
|
port (a, b : in std_logic_vector(15 downto 0); sel : in std_logic; cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
component add16
|
||||||
|
port (a, b : in std_logic_vector(15 downto 0); cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal zeroX, zeroXNot, negateX, zeroY, zeroYNot, negateY, negateXAndnegateY, bitwiseAnd, addition, whichF, whichFNot, negateOut : std_logic_vector(15 downto 0);
|
||||||
|
constant zeros : std_logic_vector(15 downto 0) := "0000000000000000";
|
||||||
|
begin
|
||||||
|
zeroXMux: mux16 port map (x, zeros, zx, zeroX);
|
||||||
|
zeroXNot <= not zeroX;
|
||||||
|
negateXMux: mux16 port map (zeroX, zeroXNot, nx, negateX);
|
||||||
|
|
||||||
|
zeroYMux: mux16 port map (y, zeros, zy, zeroY);
|
||||||
|
zeroYNot <= not zeroY;
|
||||||
|
negateYMux: mux16 port map (zeroY, zeroYNot, ny, negateY);
|
||||||
|
|
||||||
|
fAdd: add16 port map (negateX, negateY, addition);
|
||||||
|
negateXAndNegateY <= negateX and negateY;
|
||||||
|
whichFMux: mux16 port map (negateXAndNegateY, addition, f, whichF);
|
||||||
|
|
||||||
|
whichFNot <= not whichF;
|
||||||
|
negateOutMux: mux16 port map (whichF, whichFNot, no, negateOut);
|
||||||
|
|
||||||
|
cout <= negateOut;
|
||||||
|
zr <= '1' when negateOut = zeros else '0';
|
||||||
|
ng <= negateOut(15);
|
||||||
|
end alu_arch;
|
96
src/alu_tb.vhdl
Normal file
96
src/alu_tb.vhdl
Normal file
@ -0,0 +1,96 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity alu_tb is
|
||||||
|
end alu_tb;
|
||||||
|
|
||||||
|
architecture alu_tb_arch of alu_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component alu
|
||||||
|
port (x, y : in std_logic_vector(15 downto 0); zx, nx, zy, ny, f, no : in std_logic; cout : out std_logic_vector(15 downto 0); zr, ng : out std_logic);
|
||||||
|
end component;
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for alu_0: alu use entity work.alu;
|
||||||
|
signal x, y, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal zx, nx, zy, ny, f, no, zr, ng : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
alu_0: alu port map (x, y, zx, nx, zy, ny, f, no, cout, zr, ng);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the alu.
|
||||||
|
x, y : std_logic_vector(15 downto 0);
|
||||||
|
zx, nx, zy, ny, f, no : std_logic;
|
||||||
|
-- The expected outputs of the alu.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
zr, ng : std_logic;
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", "1111111111111111", '1', '0', '1', '0', '1', '0', "0000000000000000", '1', '0'),
|
||||||
|
("0000000000000000", "1111111111111111", '1', '1', '1', '1', '1', '1', "0000000000000001", '0', '0'),
|
||||||
|
("0000000000000000", "1111111111111111", '1', '1', '1', '0', '1', '0', "1111111111111111", '0', '1'),
|
||||||
|
("0000000000000000", "1111111111111111", '0', '0', '1', '1', '0', '0', "0000000000000000", '1', '0'),
|
||||||
|
("0000000000000000", "1111111111111111", '1', '1', '0', '0', '0', '0', "1111111111111111", '0', '1'),
|
||||||
|
("0000000000000000", "1111111111111111", '0', '0', '1', '1', '0', '1', "1111111111111111", '0', '1'),
|
||||||
|
("0000000000000000", "1111111111111111", '1', '1', '0', '0', '0', '1', "0000000000000000", '1', '0'),
|
||||||
|
("0000000000000000", "1111111111111111", '0', '0', '1', '1', '1', '1', "0000000000000000", '1', '0'),
|
||||||
|
("0000000000000000", "1111111111111111", '1', '1', '0', '0', '1', '1', "0000000000000001", '0', '0'),
|
||||||
|
("0000000000000000", "1111111111111111", '0', '1', '1', '1', '1', '1', "0000000000000001", '0', '0'),
|
||||||
|
("0000000000000000", "1111111111111111", '1', '1', '0', '1', '1', '1', "0000000000000000", '1', '0'),
|
||||||
|
("0000000000000000", "1111111111111111", '0', '0', '1', '1', '1', '0', "1111111111111111", '0', '1'),
|
||||||
|
("0000000000000000", "1111111111111111", '1', '1', '0', '0', '1', '0', "1111111111111110", '0', '1'),
|
||||||
|
("0000000000000000", "1111111111111111", '0', '0', '0', '0', '1', '0', "1111111111111111", '0', '1'),
|
||||||
|
("0000000000000000", "1111111111111111", '0', '1', '0', '0', '1', '1', "0000000000000001", '0', '0'),
|
||||||
|
("0000000000000000", "1111111111111111", '0', '0', '0', '1', '1', '1', "1111111111111111", '0', '1'),
|
||||||
|
("0000000000000000", "1111111111111111", '0', '0', '0', '0', '0', '0', "0000000000000000", '1', '0'),
|
||||||
|
("0000000000000000", "1111111111111111", '0', '1', '0', '1', '0', '1', "1111111111111111", '0', '1'),
|
||||||
|
("0000000000010001", "0000000000000011", '1', '0', '1', '0', '1', '0', "0000000000000000", '1', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '1', '1', '1', '1', '1', '1', "0000000000000001", '0', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '1', '1', '1', '0', '1', '0', "1111111111111111", '0', '1'),
|
||||||
|
("0000000000010001", "0000000000000011", '0', '0', '1', '1', '0', '0', "0000000000010001", '0', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '1', '1', '0', '0', '0', '0', "0000000000000011", '0', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '0', '0', '1', '1', '0', '1', "1111111111101110", '0', '1'),
|
||||||
|
("0000000000010001", "0000000000000011", '1', '1', '0', '0', '0', '1', "1111111111111100", '0', '1'),
|
||||||
|
("0000000000010001", "0000000000000011", '0', '0', '1', '1', '1', '1', "1111111111101111", '0', '1'),
|
||||||
|
("0000000000010001", "0000000000000011", '1', '1', '0', '0', '1', '1', "1111111111111101", '0', '1'),
|
||||||
|
("0000000000010001", "0000000000000011", '0', '1', '1', '1', '1', '1', "0000000000010010", '0', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '1', '1', '0', '1', '1', '1', "0000000000000100", '0', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '0', '0', '1', '1', '1', '0', "0000000000010000", '0', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '1', '1', '0', '0', '1', '0', "0000000000000010", '0', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '0', '0', '0', '0', '1', '0', "0000000000010100", '0', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '0', '1', '0', '0', '1', '1', "0000000000001110", '0', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '0', '0', '0', '1', '1', '1', "1111111111110010", '0', '1'),
|
||||||
|
("0000000000010001", "0000000000000011", '0', '0', '0', '0', '0', '0', "0000000000000001", '0', '0'),
|
||||||
|
("0000000000010001", "0000000000000011", '0', '1', '0', '1', '0', '1', "0000000000010011", '0', '0'));
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
x <= patterns(i).x;
|
||||||
|
y <= patterns(i).y;
|
||||||
|
zx <= patterns(i).zx;
|
||||||
|
nx <= patterns(i).nx;
|
||||||
|
zy <= patterns(i).zy;
|
||||||
|
ny <= patterns(i).ny;
|
||||||
|
f <= patterns(i).f;
|
||||||
|
no <= patterns(i).no;
|
||||||
|
-- Wait for the results.
|
||||||
|
wait for 1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad alu output" severity error;
|
||||||
|
assert zr = patterns(i).zr
|
||||||
|
report "bad alu zr control bit output" severity error;
|
||||||
|
assert ng = patterns(i).ng
|
||||||
|
report "bad alu ng control bit output" severity error;
|
||||||
|
end loop;
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end alu_tb_arch;
|
16
src/clock.vhdl
Normal file
16
src/clock.vhdl
Normal file
@ -0,0 +1,16 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity clock is
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end clock;
|
||||||
|
|
||||||
|
architecture clock_arch of clock is
|
||||||
|
signal clk: std_logic := '0';
|
||||||
|
begin
|
||||||
|
clk <= '0' when finish = '1' else
|
||||||
|
'1' after 0.5 ns when clk = '0' else
|
||||||
|
'0' after 0.5 ns when clk = '1';
|
||||||
|
cout <= clk;
|
||||||
|
end clock_arch;
|
93
src/clock_tb.vhdl
Normal file
93
src/clock_tb.vhdl
Normal file
@ -0,0 +1,93 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity clock_tb is
|
||||||
|
end clock_tb;
|
||||||
|
|
||||||
|
architecture clock_tb_arch of clock_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component clock
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for clock_0: clock use entity work.clock;
|
||||||
|
signal finish, cout : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
clock_0: clock port map (finish, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the clock.
|
||||||
|
finish : std_logic;
|
||||||
|
-- The output of the clock.
|
||||||
|
cout : std_logic;
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(('0', '0'),
|
||||||
|
('0', '1'),
|
||||||
|
('0', '0'),
|
||||||
|
('0', '1'),
|
||||||
|
('0', '0'),
|
||||||
|
('0', '1'),
|
||||||
|
('0', '0'),
|
||||||
|
('0', '1'),
|
||||||
|
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('0', '0'),
|
||||||
|
('0', '1'),
|
||||||
|
('0', '0'),
|
||||||
|
('0', '1'),
|
||||||
|
|
||||||
|
('0', '0'),
|
||||||
|
('0', '1'),
|
||||||
|
('0', '0'),
|
||||||
|
('0', '1'),
|
||||||
|
('0', '0'),
|
||||||
|
('0', '1'),
|
||||||
|
('0', '0'),
|
||||||
|
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('1', '0'),
|
||||||
|
('0', '0'),
|
||||||
|
('0', '1'),
|
||||||
|
('0', '0'),
|
||||||
|
('0', '1'));
|
||||||
|
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
finish <= patterns(i).finish;
|
||||||
|
wait for 0.1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad clock" severity error;
|
||||||
|
wait for 0.4 ns;
|
||||||
|
end loop;
|
||||||
|
-- End the clock
|
||||||
|
finish <= '1';
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end clock_tb_arch;
|
22
src/dbit.vhdl
Normal file
22
src/dbit.vhdl
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity dbit is
|
||||||
|
port (d, load, clk : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end dbit;
|
||||||
|
|
||||||
|
architecture dbit_arch of dbit is
|
||||||
|
component mux
|
||||||
|
port (a, b, sel : in std_logic; cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
component dff
|
||||||
|
port (d, clk : in std_logic; cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal dffOut, muxOut : std_logic;
|
||||||
|
begin
|
||||||
|
MUX_0: mux port map (dffOut, d, load, muxOut);
|
||||||
|
DFF_0: dff port map (muxOut, clk, dffOut);
|
||||||
|
cout <= dffOut;
|
||||||
|
end dbit_arch;
|
272
src/dbit_tb.vhdl
Normal file
272
src/dbit_tb.vhdl
Normal file
@ -0,0 +1,272 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity dbit_tb is
|
||||||
|
end dbit_tb;
|
||||||
|
|
||||||
|
architecture dbit_tb_arch of dbit_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component dbit
|
||||||
|
port (d, load, clk : in std_logic; cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
-- Declaration of the clock
|
||||||
|
component Clock
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for dbit_0: dbit use entity work.dbit;
|
||||||
|
signal d, load, finish, clk, cout : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
OSC_CLK: Clock port map (finish, clk);
|
||||||
|
dbit_0: dbit port map (d, load, clk, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the dbit.
|
||||||
|
d, load : std_logic;
|
||||||
|
-- The output of the dbit.
|
||||||
|
cout : std_logic;
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(('0', '0', '0'),
|
||||||
|
('0', '0', '0'),
|
||||||
|
('0', '0', '0'),
|
||||||
|
('0', '1', '0'),
|
||||||
|
('0', '1', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '1', '0'),
|
||||||
|
('1', '1', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('1', '0', '1'),
|
||||||
|
('1', '0', '1'),
|
||||||
|
('0', '1', '1'),
|
||||||
|
('0', '1', '0'),
|
||||||
|
('1', '1', '0'),
|
||||||
|
('1', '1', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '0', '1'),
|
||||||
|
('0', '1', '1'),
|
||||||
|
('0', '1', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'),
|
||||||
|
('1', '0', '0'));
|
||||||
|
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
d <= patterns(i).d;
|
||||||
|
load <= patterns(i).load;
|
||||||
|
wait for 0.25 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad data; nothing remembered" severity error;
|
||||||
|
wait for 0.75 ns;
|
||||||
|
end loop;
|
||||||
|
-- End the clock
|
||||||
|
finish <= '1';
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end dbit_tb_arch;
|
13
src/dmux.vhdl
Normal file
13
src/dmux.vhdl
Normal file
@ -0,0 +1,13 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity dmux is
|
||||||
|
port (cin, sel : in std_logic;
|
||||||
|
a, b : out std_logic);
|
||||||
|
end dmux;
|
||||||
|
|
||||||
|
architecture dmux_arch of dmux is
|
||||||
|
begin
|
||||||
|
a <= cin and (not sel);
|
||||||
|
b <= cin and sel;
|
||||||
|
end dmux_arch;
|
21
src/dmux4way.vhdl
Normal file
21
src/dmux4way.vhdl
Normal file
@ -0,0 +1,21 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity dmux4way is
|
||||||
|
port (cin : in std_logic;
|
||||||
|
sel : in std_logic_vector(1 downto 0);
|
||||||
|
a, b, c, d : out std_logic);
|
||||||
|
end dmux4way;
|
||||||
|
|
||||||
|
architecture dmux4way_arch of dmux4way is
|
||||||
|
component dmux
|
||||||
|
port (cin, sel : in std_logic;
|
||||||
|
a, b : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal dm1, dm2 : std_logic;
|
||||||
|
begin
|
||||||
|
dmux_0: dmux port map (cin, sel(1), dm1, dm2);
|
||||||
|
dmux_1: dmux port map (dm1, sel(0), a, b);
|
||||||
|
dmux_2: dmux port map (dm2, sel(0), c, d);
|
||||||
|
end dmux4way_arch;
|
63
src/dmux4way_tb.vhdl
Normal file
63
src/dmux4way_tb.vhdl
Normal file
@ -0,0 +1,63 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity dmux4way_tb is
|
||||||
|
end dmux4way_tb;
|
||||||
|
|
||||||
|
architecture dmux4way_tb_arch of dmux4way_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component dmux4way
|
||||||
|
port (cin : in std_logic; sel : in std_logic_vector(1 downto 0); a, b, c, d : out std_logic);
|
||||||
|
end component;
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for dmux4way_0: dmux4way use entity work.dmux4way;
|
||||||
|
signal cin, a, b, c, d : std_logic;
|
||||||
|
signal sel : std_logic_vector(1 downto 0);
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
dmux4way_0: dmux4way port map (cin, sel, a, b, c, d);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the dmux4way.
|
||||||
|
cin : std_logic;
|
||||||
|
sel : std_logic_vector(1 downto 0);
|
||||||
|
-- The expected outputs of the dmux4way.
|
||||||
|
a, b, c, d : std_logic;
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(('0', "00", '0', '0', '0', '0'),
|
||||||
|
('0', "01", '0', '0', '0', '0'),
|
||||||
|
('0', "10", '0', '0', '0', '0'),
|
||||||
|
('0', "11", '0', '0', '0', '0'),
|
||||||
|
('1', "00", '1', '0', '0', '0'),
|
||||||
|
('1', "01", '0', '1', '0', '0'),
|
||||||
|
('1', "10", '0', '0', '1', '0'),
|
||||||
|
('1', "11", '0', '0', '0', '1'));
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
cin <= patterns(i).cin;
|
||||||
|
sel <= patterns(i).sel;
|
||||||
|
-- Wait for the results.
|
||||||
|
wait for 1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert a = patterns(i).a
|
||||||
|
report "bad dmux4way" severity error;
|
||||||
|
assert b = patterns(i).b
|
||||||
|
report "bad dmux4way" severity error;
|
||||||
|
assert c = patterns(i).c
|
||||||
|
report "bad dmux4way" severity error;
|
||||||
|
assert d = patterns(i).d
|
||||||
|
report "bad dmux4way" severity error;
|
||||||
|
end loop;
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end dmux4way_tb_arch;
|
23
src/dmux8way.vhdl
Normal file
23
src/dmux8way.vhdl
Normal file
@ -0,0 +1,23 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity dmux8way is
|
||||||
|
port (cin : in std_logic;
|
||||||
|
sel : in std_logic_vector(2 downto 0);
|
||||||
|
a, b, c, d, e, f, g, h : out std_logic);
|
||||||
|
end dmux8way;
|
||||||
|
|
||||||
|
architecture dmux8way_arch of dmux8way is
|
||||||
|
component dmux
|
||||||
|
port (cin, sel : in std_logic; a, b : out std_logic);
|
||||||
|
end component;
|
||||||
|
component dmux4way
|
||||||
|
port (cin : in std_logic; sel : in std_logic_vector(1 downto 0); a, b, c, d : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal dm0, dm1 : std_logic;
|
||||||
|
begin
|
||||||
|
dmux_0: dmux port map (cin, sel(2), dm0, dm1);
|
||||||
|
dmux4way_0: dmux4way port map (dm0, sel(1 downto 0), a, b, c, d);
|
||||||
|
dmux4way_1: dmux4way port map (dm1, sel(1 downto 0), e, f, g, h);
|
||||||
|
end dmux8way_arch;
|
79
src/dmux8way_tb.vhdl
Normal file
79
src/dmux8way_tb.vhdl
Normal file
@ -0,0 +1,79 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity dmux8way_tb is
|
||||||
|
end dmux8way_tb;
|
||||||
|
|
||||||
|
architecture dmux8way_tb_arch of dmux8way_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component dmux8way
|
||||||
|
port (cin : in std_logic; sel : in std_logic_vector(2 downto 0); a, b, c, d, e, f, g, h : out std_logic);
|
||||||
|
end component;
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for dmux8way_0: dmux8way use entity work.dmux8way;
|
||||||
|
signal cin, a, b, c, d, e, f, g, h : std_logic;
|
||||||
|
signal sel : std_logic_vector(2 downto 0);
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
dmux8way_0: dmux8way port map (cin, sel, a, b, c, d, e, f, g, h);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the dmux8way.
|
||||||
|
cin : std_logic;
|
||||||
|
sel : std_logic_vector(2 downto 0);
|
||||||
|
-- The expected outputs of the dmux8way.
|
||||||
|
a, b, c, d, e, f, g, h : std_logic;
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(('0', "000", '0', '0', '0', '0', '0', '0', '0', '0'),
|
||||||
|
('0', "001", '0', '0', '0', '0', '0', '0', '0', '0'),
|
||||||
|
('0', "010", '0', '0', '0', '0', '0', '0', '0', '0'),
|
||||||
|
('0', "011", '0', '0', '0', '0', '0', '0', '0', '0'),
|
||||||
|
('0', "100", '0', '0', '0', '0', '0', '0', '0', '0'),
|
||||||
|
('0', "101", '0', '0', '0', '0', '0', '0', '0', '0'),
|
||||||
|
('0', "110", '0', '0', '0', '0', '0', '0', '0', '0'),
|
||||||
|
('0', "111", '0', '0', '0', '0', '0', '0', '0', '0'),
|
||||||
|
('1', "000", '1', '0', '0', '0', '0', '0', '0', '0'),
|
||||||
|
('1', "001", '0', '1', '0', '0', '0', '0', '0', '0'),
|
||||||
|
('1', "010", '0', '0', '1', '0', '0', '0', '0', '0'),
|
||||||
|
('1', "011", '0', '0', '0', '1', '0', '0', '0', '0'),
|
||||||
|
('1', "100", '0', '0', '0', '0', '1', '0', '0', '0'),
|
||||||
|
('1', "101", '0', '0', '0', '0', '0', '1', '0', '0'),
|
||||||
|
('1', "110", '0', '0', '0', '0', '0', '0', '1', '0'),
|
||||||
|
('1', "111", '0', '0', '0', '0', '0', '0', '0', '1'));
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
cin <= patterns(i).cin;
|
||||||
|
sel <= patterns(i).sel;
|
||||||
|
-- Wait for the results.
|
||||||
|
wait for 1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert a = patterns(i).a
|
||||||
|
report "bad dmux8way" severity error;
|
||||||
|
assert b = patterns(i).b
|
||||||
|
report "bad dmux8way" severity error;
|
||||||
|
assert c = patterns(i).c
|
||||||
|
report "bad dmux8way" severity error;
|
||||||
|
assert d = patterns(i).d
|
||||||
|
report "bad dmux8way" severity error;
|
||||||
|
assert e = patterns(i).e
|
||||||
|
report "bad dmux8way" severity error;
|
||||||
|
assert f = patterns(i).f
|
||||||
|
report "bad dmux8way" severity error;
|
||||||
|
assert g = patterns(i).g
|
||||||
|
report "bad dmux8way" severity error;
|
||||||
|
assert h = patterns(i).h
|
||||||
|
report "bad dmux8way" severity error;
|
||||||
|
end loop;
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end dmux8way_tb_arch;
|
53
src/dmux_tb.vhdl
Normal file
53
src/dmux_tb.vhdl
Normal file
@ -0,0 +1,53 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity dmux_tb is
|
||||||
|
end dmux_tb;
|
||||||
|
|
||||||
|
architecture dmux_tb_arch of dmux_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component dmux
|
||||||
|
port (cin, sel : in std_logic; a, b : out std_logic);
|
||||||
|
end component;
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for dmux_0: dmux use entity work.dmux;
|
||||||
|
signal cin, sel, a, b : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
dmux_0: dmux port map (cin, sel, a, b);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the dmux.
|
||||||
|
cin, sel : std_logic;
|
||||||
|
-- The expected outputs of the dmux.
|
||||||
|
a, b : std_logic;
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(('0', '0', '0', '0'),
|
||||||
|
('0', '1', '0', '0'),
|
||||||
|
('1', '0', '1', '0'),
|
||||||
|
('1', '1', '0', '1'));
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
cin <= patterns(i).cin;
|
||||||
|
sel <= patterns(i).sel;
|
||||||
|
-- Wait for the results.
|
||||||
|
wait for 1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert a = patterns(i).a
|
||||||
|
report "bad dmux" severity error;
|
||||||
|
assert b = patterns(i).b
|
||||||
|
report "bad dmux" severity error;
|
||||||
|
end loop;
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end dmux_tb_arch;
|
18
src/dregister.vhdl
Normal file
18
src/dregister.vhdl
Normal file
@ -0,0 +1,18 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity dregister is
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load, clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end dregister;
|
||||||
|
|
||||||
|
architecture dregister_arch of dregister is
|
||||||
|
component dbit
|
||||||
|
port (d, load, clk : in std_logic; cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
begin
|
||||||
|
reg: for i in 0 to 15 generate
|
||||||
|
dbit_i: dbit port map (d(i), load, clk, cout(i));
|
||||||
|
end generate;
|
||||||
|
end dregister_arch;
|
207
src/dregister_tb.vhdl
Normal file
207
src/dregister_tb.vhdl
Normal file
@ -0,0 +1,207 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity dregister_tb is
|
||||||
|
end dregister_tb;
|
||||||
|
|
||||||
|
architecture dregister_tb_arch of dregister_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component dregister
|
||||||
|
port (d : in std_logic_vector(15 downto 0); load, clk : in std_logic; cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Declaration of the clock
|
||||||
|
component Clock
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for dregister_0: dregister use entity work.dregister;
|
||||||
|
signal d, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal load, finish, clk : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
OSC_CLK: Clock port map (finish, clk);
|
||||||
|
dregister_0: dregister port map (d, load, clk, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the dregister.
|
||||||
|
d : std_logic_vector(15 downto 0);
|
||||||
|
load : std_logic;
|
||||||
|
-- The output of the dregister.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", '0', "0000000000000000"),
|
||||||
|
("0000000000000000", '0', "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "0000000000000000"),
|
||||||
|
("0111110101111011", '0', "0000000000000000"),
|
||||||
|
("0111110101111011", '0', "0000000000000000"),
|
||||||
|
("0010101101100111", '0', "0000000000000000"),
|
||||||
|
("0010101101100111", '0', "0000000000000000"),
|
||||||
|
("0111110101111011", '1', "0000000000000000"),
|
||||||
|
("0111110101111011", '1', "0111110101111011"),
|
||||||
|
("0111110101111011", '1', "0111110101111011"),
|
||||||
|
("0111110101111011", '1', "0111110101111011"),
|
||||||
|
("0111110101111011", '0', "0111110101111011"),
|
||||||
|
("0111110101111011", '0', "0111110101111011"),
|
||||||
|
("0011000000111001", '1', "0111110101111011"),
|
||||||
|
("0011000000111001", '1', "0011000000111001"),
|
||||||
|
("0000000000000000", '0', "0011000000111001"),
|
||||||
|
("0000000000000000", '0', "0011000000111001"),
|
||||||
|
("0000000000000000", '1', "0011000000111001"),
|
||||||
|
("0000000000000000", '1', "0000000000000000"),
|
||||||
|
("0000000000000001", '0', "0000000000000000"),
|
||||||
|
("0000000000000001", '0', "0000000000000000"),
|
||||||
|
("0000000000000001", '1', "0000000000000000"),
|
||||||
|
("0000000000000001", '1', "0000000000000001"),
|
||||||
|
("0000000000000010", '0', "0000000000000001"),
|
||||||
|
("0000000000000010", '0', "0000000000000001"),
|
||||||
|
("0000000000000010", '1', "0000000000000001"),
|
||||||
|
("0000000000000010", '1', "0000000000000010"),
|
||||||
|
("0000000000000100", '0', "0000000000000010"),
|
||||||
|
("0000000000000100", '0', "0000000000000010"),
|
||||||
|
("0000000000000100", '1', "0000000000000010"),
|
||||||
|
("0000000000000100", '1', "0000000000000100"),
|
||||||
|
("0000000000001000", '0', "0000000000000100"),
|
||||||
|
("0000000000001000", '0', "0000000000000100"),
|
||||||
|
("0000000000001000", '1', "0000000000000100"),
|
||||||
|
("0000000000001000", '1', "0000000000001000"),
|
||||||
|
("0000000000010000", '0', "0000000000001000"),
|
||||||
|
("0000000000010000", '0', "0000000000001000"),
|
||||||
|
("0000000000010000", '1', "0000000000001000"),
|
||||||
|
("0000000000010000", '1', "0000000000010000"),
|
||||||
|
("0000000000100000", '0', "0000000000010000"),
|
||||||
|
("0000000000100000", '0', "0000000000010000"),
|
||||||
|
("0000000000100000", '1', "0000000000010000"),
|
||||||
|
("0000000000100000", '1', "0000000000100000"),
|
||||||
|
("0000000001000000", '0', "0000000000100000"),
|
||||||
|
("0000000001000000", '0', "0000000000100000"),
|
||||||
|
("0000000001000000", '1', "0000000000100000"),
|
||||||
|
("0000000001000000", '1', "0000000001000000"),
|
||||||
|
("0000000010000000", '0', "0000000001000000"),
|
||||||
|
("0000000010000000", '0', "0000000001000000"),
|
||||||
|
("0000000010000000", '1', "0000000001000000"),
|
||||||
|
("0000000010000000", '1', "0000000010000000"),
|
||||||
|
("0000000100000000", '0', "0000000010000000"),
|
||||||
|
("0000000100000000", '0', "0000000010000000"),
|
||||||
|
("0000000100000000", '1', "0000000010000000"),
|
||||||
|
("0000000100000000", '1', "0000000100000000"),
|
||||||
|
("0000001000000000", '0', "0000000100000000"),
|
||||||
|
("0000001000000000", '0', "0000000100000000"),
|
||||||
|
("0000001000000000", '1', "0000000100000000"),
|
||||||
|
("0000001000000000", '1', "0000001000000000"),
|
||||||
|
("0000010000000000", '0', "0000001000000000"),
|
||||||
|
("0000010000000000", '0', "0000001000000000"),
|
||||||
|
("0000010000000000", '1', "0000001000000000"),
|
||||||
|
("0000010000000000", '1', "0000010000000000"),
|
||||||
|
("0000100000000000", '0', "0000010000000000"),
|
||||||
|
("0000100000000000", '0', "0000010000000000"),
|
||||||
|
("0000100000000000", '1', "0000010000000000"),
|
||||||
|
("0000100000000000", '1', "0000100000000000"),
|
||||||
|
("0001000000000000", '0', "0000100000000000"),
|
||||||
|
("0001000000000000", '0', "0000100000000000"),
|
||||||
|
("0001000000000000", '1', "0000100000000000"),
|
||||||
|
("0001000000000000", '1', "0001000000000000"),
|
||||||
|
("0010000000000000", '0', "0001000000000000"),
|
||||||
|
("0010000000000000", '0', "0001000000000000"),
|
||||||
|
("0010000000000000", '1', "0001000000000000"),
|
||||||
|
("0010000000000000", '1', "0010000000000000"),
|
||||||
|
("0100000000000000", '0', "0010000000000000"),
|
||||||
|
("0100000000000000", '0', "0010000000000000"),
|
||||||
|
("0100000000000000", '1', "0010000000000000"),
|
||||||
|
("0100000000000000", '1', "0100000000000000"),
|
||||||
|
("1000000000000000", '0', "0100000000000000"),
|
||||||
|
("1000000000000000", '0', "0100000000000000"),
|
||||||
|
("1000000000000000", '1', "0100000000000000"),
|
||||||
|
("1000000000000000", '1', "1000000000000000"),
|
||||||
|
("0000000000000010", '0', "1000000000000000"),
|
||||||
|
("0000000000000010", '0', "1000000000000000"),
|
||||||
|
("0000000000000010", '1', "1000000000000000"),
|
||||||
|
("0000000000000010", '1', "0000000000000010"),
|
||||||
|
("0000000000000011", '0', "0000000000000010"),
|
||||||
|
("0000000000000011", '0', "0000000000000010"),
|
||||||
|
("0000000000000011", '1', "0000000000000010"),
|
||||||
|
("0000000000000011", '1', "0000000000000011"),
|
||||||
|
("0000000000000101", '0', "0000000000000011"),
|
||||||
|
("0000000000000101", '0', "0000000000000011"),
|
||||||
|
("0000000000000101", '1', "0000000000000011"),
|
||||||
|
("0000000000000101", '1', "0000000000000101"),
|
||||||
|
("0000000000001001", '0', "0000000000000101"),
|
||||||
|
("0000000000001001", '0', "0000000000000101"),
|
||||||
|
("0000000000001001", '1', "0000000000000101"),
|
||||||
|
("0000000000001001", '1', "0000000000001001"),
|
||||||
|
("0000000000010001", '0', "0000000000001001"),
|
||||||
|
("0000000000010001", '0', "0000000000001001"),
|
||||||
|
("0000000000010001", '1', "0000000000001001"),
|
||||||
|
("0000000000010001", '1', "0000000000010001"),
|
||||||
|
("0000000000100001", '0', "0000000000010001"),
|
||||||
|
("0000000000100001", '0', "0000000000010001"),
|
||||||
|
("0000000000100001", '1', "0000000000010001"),
|
||||||
|
("0000000000100001", '1', "0000000000100001"),
|
||||||
|
("0000000001000001", '0', "0000000000100001"),
|
||||||
|
("0000000001000001", '0', "0000000000100001"),
|
||||||
|
("0000000001000001", '1', "0000000000100001"),
|
||||||
|
("0000000001000001", '1', "0000000001000001"),
|
||||||
|
("0000000010000001", '0', "0000000001000001"),
|
||||||
|
("0000000010000001", '0', "0000000001000001"),
|
||||||
|
("0000000010000001", '1', "0000000001000001"),
|
||||||
|
("0000000010000001", '1', "0000000010000001"),
|
||||||
|
("0000000100000001", '0', "0000000010000001"),
|
||||||
|
("0000000100000001", '0', "0000000010000001"),
|
||||||
|
("0000000100000001", '1', "0000000010000001"),
|
||||||
|
("0000000100000001", '1', "0000000100000001"),
|
||||||
|
("0000001000000001", '0', "0000000100000001"),
|
||||||
|
("0000001000000001", '0', "0000000100000001"),
|
||||||
|
("0000001000000001", '1', "0000000100000001"),
|
||||||
|
("0000001000000001", '1', "0000001000000001"),
|
||||||
|
("0000010000000001", '0', "0000001000000001"),
|
||||||
|
("0000010000000001", '0', "0000001000000001"),
|
||||||
|
("0000010000000001", '1', "0000001000000001"),
|
||||||
|
("0000010000000001", '1', "0000010000000001"),
|
||||||
|
("0000100000000001", '0', "0000010000000001"),
|
||||||
|
("0000100000000001", '0', "0000010000000001"),
|
||||||
|
("0000100000000001", '1', "0000010000000001"),
|
||||||
|
("0000100000000001", '1', "0000100000000001"),
|
||||||
|
("0001000000000001", '0', "0000100000000001"),
|
||||||
|
("0001000000000001", '0', "0000100000000001"),
|
||||||
|
("0001000000000001", '1', "0000100000000001"),
|
||||||
|
("0001000000000001", '1', "0001000000000001"),
|
||||||
|
("0010000000000001", '0', "0001000000000001"),
|
||||||
|
("0010000000000001", '0', "0001000000000001"),
|
||||||
|
("0010000000000001", '1', "0001000000000001"),
|
||||||
|
("0010000000000001", '1', "0010000000000001"),
|
||||||
|
("0100000000000001", '0', "0010000000000001"),
|
||||||
|
("0100000000000001", '0', "0010000000000001"),
|
||||||
|
("0100000000000001", '1', "0010000000000001"),
|
||||||
|
("0100000000000001", '1', "0100000000000001"),
|
||||||
|
("0111111111111111", '0', "0100000000000001"),
|
||||||
|
("0111111111111111", '0', "0100000000000001"),
|
||||||
|
("0111111111111111", '1', "0100000000000001"),
|
||||||
|
("0111111111111111", '1', "0111111111111111"));
|
||||||
|
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
d <= patterns(i).d;
|
||||||
|
load <= patterns(i).load;
|
||||||
|
wait for 0.25 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad data; nothing remembered" severity error;
|
||||||
|
wait for 0.75 ns;
|
||||||
|
end loop;
|
||||||
|
-- End the clock
|
||||||
|
finish <= '1';
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end dregister_tb_arch;
|
12
src/mux.vhdl
Normal file
12
src/mux.vhdl
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity mux is
|
||||||
|
port (a, b, sel : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end mux;
|
||||||
|
|
||||||
|
architecture mux_arch of mux is
|
||||||
|
begin
|
||||||
|
cout <= a when sel='0' else b;
|
||||||
|
end mux_arch;
|
13
src/mux16.vhdl
Normal file
13
src/mux16.vhdl
Normal file
@ -0,0 +1,13 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity mux16 is
|
||||||
|
port (a, b : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end mux16;
|
||||||
|
|
||||||
|
architecture mux16_arch of mux16 is
|
||||||
|
begin
|
||||||
|
cout <= a when sel='0' else b;
|
||||||
|
end mux16_arch;
|
60
src/mux16_tb.vhdl
Normal file
60
src/mux16_tb.vhdl
Normal file
@ -0,0 +1,60 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity mux16_tb is
|
||||||
|
end mux16_tb;
|
||||||
|
|
||||||
|
architecture mux16_tb_arch of mux16_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component mux16
|
||||||
|
port (a, b : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for mux16_0: mux16 use entity work.mux16;
|
||||||
|
signal a, b, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal sel : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
mux16_0: mux16 port map (a => a, b => b, sel => sel, cout => cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the mux16.
|
||||||
|
a, b : std_logic_vector(15 downto 0);
|
||||||
|
sel : std_logic;
|
||||||
|
-- The expected outputs of the mux16.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", "0000000000000001", '0', "0000000000000000"),
|
||||||
|
("0000000000000001", "0000000000000000", '1', "0000000000000000"),
|
||||||
|
("0000000000000000", "1111111111111111", '0', "0000000000000000"),
|
||||||
|
("0000000000000000", "1111111111111111", '1', "1111111111111111"),
|
||||||
|
("1111111111111111", "0000000000000000", '0', "1111111111111111"),
|
||||||
|
("1111111111111111", "0000000000000000", '1', "0000000000000000"),
|
||||||
|
("1111111111111111", "1111111111111110", '0', "1111111111111111"),
|
||||||
|
("1111111111111110", "1111111111111111", '1', "1111111111111111"));
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
a <= patterns(i).a;
|
||||||
|
b <= patterns(i).b;
|
||||||
|
sel <= patterns(i).sel;
|
||||||
|
-- Wait for the results.
|
||||||
|
wait for 1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad mux16 output" severity error;
|
||||||
|
end loop;
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end mux16_tb_arch;
|
22
src/mux4way16.vhdl
Normal file
22
src/mux4way16.vhdl
Normal file
@ -0,0 +1,22 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity mux4way16 is
|
||||||
|
port (a, b, c, d : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(1 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end mux4way16;
|
||||||
|
|
||||||
|
architecture mux4way16_arch of mux4way16 is
|
||||||
|
component mux16
|
||||||
|
port (a, b : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal mx0, mx1 : std_logic_vector(15 downto 0);
|
||||||
|
begin
|
||||||
|
mux16_0: mux16 port map (a, b, sel(0), mx0);
|
||||||
|
mux16_1: mux16 port map (c, d, sel(0), mx1);
|
||||||
|
mux16_2: mux16 port map (mx0, mx1, sel(1), cout);
|
||||||
|
end mux4way16_arch;
|
62
src/mux4way16_tb.vhdl
Normal file
62
src/mux4way16_tb.vhdl
Normal file
@ -0,0 +1,62 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity mux4way16_tb is
|
||||||
|
end mux4way16_tb;
|
||||||
|
|
||||||
|
architecture mux4way16_tb_arch of mux4way16_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component mux4way16
|
||||||
|
port (a, b, c, d : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(1 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for mux4way16_0: mux4way16 use entity work.mux4way16;
|
||||||
|
signal a, b, c, d, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal sel : std_logic_vector(1 downto 0);
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
mux4way16_0: mux4way16 port map (a, b, c, d, sel, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the mux4way16.
|
||||||
|
a, b, c, d : std_logic_vector(15 downto 0);
|
||||||
|
sel : std_logic_vector(1 downto 0);
|
||||||
|
-- The expected outputs of the mux4way16.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "00", "0000000000000000"),
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "01", "0000000000000000"),
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "10", "0000000000000000"),
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "11", "0000000000000000"),
|
||||||
|
("0001001000110100", "1001100001110110", "1010101010101010", "0101010101010101", "00", "0001001000110100"),
|
||||||
|
("0001001000110100", "1001100001110110", "1010101010101010", "0101010101010101", "01", "1001100001110110"),
|
||||||
|
("0001001000110100", "1001100001110110", "1010101010101010", "0101010101010101", "10", "1010101010101010"),
|
||||||
|
("0001001000110100", "1001100001110110", "1010101010101010", "0101010101010101", "11", "0101010101010101"));
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
a <= patterns(i).a;
|
||||||
|
b <= patterns(i).b;
|
||||||
|
c <= patterns(i).c;
|
||||||
|
d <= patterns(i).d;
|
||||||
|
sel <= patterns(i).sel;
|
||||||
|
-- Wait for the results.
|
||||||
|
wait for 1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad mux4way16 output" severity error;
|
||||||
|
end loop;
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end mux4way16_tb_arch;
|
27
src/mux8way16.vhdl
Normal file
27
src/mux8way16.vhdl
Normal file
@ -0,0 +1,27 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity mux8way16 is
|
||||||
|
port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(2 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end mux8way16;
|
||||||
|
|
||||||
|
architecture mux8way16_arch of mux8way16 is
|
||||||
|
component mux16
|
||||||
|
port (a, b : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
component mux4way16
|
||||||
|
port (a, b, c, d : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(1 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal mx0, mx1 : std_logic_vector(15 downto 0);
|
||||||
|
begin
|
||||||
|
mux4way16_0: mux4way16 port map (a, b, c, d, sel(1 downto 0), mx0);
|
||||||
|
mux4way16_1: mux4way16 port map (e, f, g, h, sel(1 downto 0), mx1);
|
||||||
|
mux16_0: mux16 port map (mx0, mx1, sel(2), cout);
|
||||||
|
end mux8way16_arch;
|
74
src/mux8way16_tb.vhdl
Normal file
74
src/mux8way16_tb.vhdl
Normal file
@ -0,0 +1,74 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity mux8way16_tb is
|
||||||
|
end mux8way16_tb;
|
||||||
|
|
||||||
|
architecture mux8way16_tb_arch of mux8way16_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component mux8way16
|
||||||
|
port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(2 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for mux8way16_0: mux8way16 use entity work.mux8way16;
|
||||||
|
signal a, b, c, d, e, f, g, h, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal sel : std_logic_vector(2 downto 0);
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
mux8way16_0: mux8way16 port map (a, b, c, d, e, f, g, h, sel, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the mux8way16.
|
||||||
|
a, b, c, d, e, f, g, h : std_logic_vector(15 downto 0);
|
||||||
|
sel : std_logic_vector(2 downto 0);
|
||||||
|
-- The expected outputs of the mux8way16.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "000", "0000000000000000"),
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "001", "0000000000000000"),
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "010", "0000000000000000"),
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "011", "0000000000000000"),
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "100", "0000000000000000"),
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "101", "0000000000000000"),
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "110", "0000000000000000"),
|
||||||
|
("0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "0000000000000000", "111", "0000000000000000"),
|
||||||
|
("0001001000110100", "0010001101000101", "0011010001010110", "0100010101100111", "0101011001111000", "0110011110001001", "0111100010011010", "1000100110101011", "000", "0001001000110100"),
|
||||||
|
("0001001000110100", "0010001101000101", "0011010001010110", "0100010101100111", "0101011001111000", "0110011110001001", "0111100010011010", "1000100110101011", "001", "0010001101000101"),
|
||||||
|
("0001001000110100", "0010001101000101", "0011010001010110", "0100010101100111", "0101011001111000", "0110011110001001", "0111100010011010", "1000100110101011", "010", "0011010001010110"),
|
||||||
|
("0001001000110100", "0010001101000101", "0011010001010110", "0100010101100111", "0101011001111000", "0110011110001001", "0111100010011010", "1000100110101011", "011", "0100010101100111"),
|
||||||
|
("0001001000110100", "0010001101000101", "0011010001010110", "0100010101100111", "0101011001111000", "0110011110001001", "0111100010011010", "1000100110101011", "100", "0101011001111000"),
|
||||||
|
("0001001000110100", "0010001101000101", "0011010001010110", "0100010101100111", "0101011001111000", "0110011110001001", "0111100010011010", "1000100110101011", "101", "0110011110001001"),
|
||||||
|
("0001001000110100", "0010001101000101", "0011010001010110", "0100010101100111", "0101011001111000", "0110011110001001", "0111100010011010", "1000100110101011", "110", "0111100010011010"),
|
||||||
|
("0001001000110100", "0010001101000101", "0011010001010110", "0100010101100111", "0101011001111000", "0110011110001001", "0111100010011010", "1000100110101011", "111", "1000100110101011"));
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
a <= patterns(i).a;
|
||||||
|
b <= patterns(i).b;
|
||||||
|
c <= patterns(i).c;
|
||||||
|
d <= patterns(i).d;
|
||||||
|
e <= patterns(i).e;
|
||||||
|
f <= patterns(i).f;
|
||||||
|
g <= patterns(i).g;
|
||||||
|
h <= patterns(i).h;
|
||||||
|
sel <= patterns(i).sel;
|
||||||
|
-- Wait for the results.
|
||||||
|
wait for 1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad mux8way16 output" severity error;
|
||||||
|
end loop;
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end mux8way16_tb_arch;
|
56
src/mux_tb.vhdl
Normal file
56
src/mux_tb.vhdl
Normal file
@ -0,0 +1,56 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity mux_tb is
|
||||||
|
end mux_tb;
|
||||||
|
|
||||||
|
architecture mux_tb_arch of mux_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component mux
|
||||||
|
port (a, b, sel : in std_logic; cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for mux_0: mux use entity work.mux;
|
||||||
|
signal a, b, sel, cout : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
mux_0: mux port map (a => a, b => b, sel => sel, cout => cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the mux.
|
||||||
|
a, b, sel : std_logic;
|
||||||
|
-- The expected outputs of the mux.
|
||||||
|
cout : std_logic;
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(('0', '0', '0', '0'),
|
||||||
|
('0', '0', '1', '0'),
|
||||||
|
('0', '1', '0', '0'),
|
||||||
|
('0', '1', '1', '1'),
|
||||||
|
('1', '0', '0', '1'),
|
||||||
|
('1', '0', '1', '0'),
|
||||||
|
('1', '1', '0', '1'),
|
||||||
|
('1', '1', '1', '1'));
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
a <= patterns(i).a;
|
||||||
|
b <= patterns(i).b;
|
||||||
|
sel <= patterns(i).sel;
|
||||||
|
-- Wait for the results.
|
||||||
|
wait for 1 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad mux output" severity error;
|
||||||
|
end loop;
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end mux_tb_arch;
|
46
src/pc.vhdl
Normal file
46
src/pc.vhdl
Normal file
@ -0,0 +1,46 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
|
entity pc is
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load, inc, reset, clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end pc;
|
||||||
|
|
||||||
|
architecture pc_arch of pc is
|
||||||
|
component dregister
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load, clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
component mux8way16
|
||||||
|
port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(2 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
component add16
|
||||||
|
port (a, b : std_logic_vector(15 downto 0); cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal regLoad : std_logic;
|
||||||
|
signal regOut, regOutInc, coutT : std_logic_vector(15 downto 0);
|
||||||
|
signal muxsel : std_logic_vector(2 downto 0);
|
||||||
|
|
||||||
|
constant zeroes : std_logic_vector(15 downto 0) := "0000000000000000";
|
||||||
|
begin
|
||||||
|
muxsel <= reset & load & inc;
|
||||||
|
regLoad <= load or inc or reset;
|
||||||
|
add16_0: add16 port map ("0000000000000001", regOut, regOutInc);
|
||||||
|
|
||||||
|
-- regOutInc <= std_logic_vector(unsigned(regOut) + 1);
|
||||||
|
--coutT <= "0000000000000000" when (reset = '1') else
|
||||||
|
-- d when (load = '1') else
|
||||||
|
-- regOutInc when (inc = '1') else
|
||||||
|
-- regOut;
|
||||||
|
|
||||||
|
mux8way16_0: mux8way16 port map (regOut, regOutInc, d, d, zeroes, zeroes, zeroes, zeroes, muxsel, coutT);
|
||||||
|
reg_0: dregister port map (coutT, regLoad, clk, regOut);
|
||||||
|
|
||||||
|
cout <= regOut;
|
||||||
|
end pc_arch;
|
119
src/pc_tb.vhdl
Normal file
119
src/pc_tb.vhdl
Normal file
@ -0,0 +1,119 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity pc_tb is
|
||||||
|
end pc_tb;
|
||||||
|
|
||||||
|
architecture pc_tb_arch of pc_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component pc
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load, inc, reset, clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Declaration of the clock
|
||||||
|
component Clock
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for pc_0: pc use entity work.pc;
|
||||||
|
signal d, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal load, inc, reset, finish, clk : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
OSC_CLK: Clock port map (finish, clk);
|
||||||
|
pc_0: pc port map (d, load, inc, reset, clk, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the pc.
|
||||||
|
d : std_logic_vector(15 downto 0);
|
||||||
|
reset, load, inc : std_logic;
|
||||||
|
-- The output of the pc.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", '0', '0', '0', "0000000000000000"), -- 0
|
||||||
|
("0000000000000000", '0', '0', '0', "0000000000000000"), -- 1
|
||||||
|
("0000000000000000", '0', '0', '1', "0000000000000000"), -- 2
|
||||||
|
("0000000000000000", '0', '0', '1', "0000000000000001"), -- 3
|
||||||
|
|
||||||
|
("0111110101111011", '0', '0', '1', "0000000000000010"), -- 4 (revised)
|
||||||
|
("0111110101111011", '0', '0', '1', "0000000000000011"), -- 5 (revised)
|
||||||
|
("0111110101111011", '0', '1', '1', "0000000000000100"), -- 6 (revised)
|
||||||
|
-- ("0111110101111011", '0', '0', '1', "0000000000000001"), -- 4 (here)
|
||||||
|
-- ("0111110101111011", '0', '0', '1', "0000000000000010"), -- 5 (here)
|
||||||
|
-- ("0111110101111011", '0', '1', '1', "0000000000000010"), -- 6 (here)
|
||||||
|
|
||||||
|
("0111110101111011", '0', '1', '1', "0111110101111011"), -- 7
|
||||||
|
("0111110101111011", '0', '0', '1', "0111110101111011"), -- 8
|
||||||
|
|
||||||
|
("0111110101111011", '0', '0', '1', "0111110101111100"), -- 9 (revised)
|
||||||
|
("0111110101111011", '0', '0', '1', "0111110101111101"), -- 10 (revised)
|
||||||
|
("0111110101111011", '0', '0', '1', "0111110101111110"), -- 11 (revised)
|
||||||
|
("0011000000111001", '0', '1', '0', "0111110101111111"), -- 12 (revised)
|
||||||
|
-- ("0111110101111011", '0', '0', '1', "0111110101111010"), -- 9 (here)
|
||||||
|
-- ("0111110101111011", '0', '0', '1', "0111110101111010"), -- 10 (here)
|
||||||
|
-- ("0111110101111011", '0', '0', '1', "0111110101111001"), -- 11 (here)
|
||||||
|
-- ("0011000000111001", '0', '1', '0', "0111110101111001"), -- 12 (here)
|
||||||
|
|
||||||
|
("0011000000111001", '0', '1', '0', "0011000000111001"), -- 13
|
||||||
|
("0011000000111001", '1', '1', '0', "0011000000111001"), -- 14
|
||||||
|
("0011000000111001", '1', '1', '0', "0000000000000000"), -- 15
|
||||||
|
("0011000000111001", '0', '1', '1', "0000000000000000"), -- 16
|
||||||
|
("0011000000111001", '0', '1', '1', "0011000000111001"), -- 17
|
||||||
|
("0011000000111001", '1', '1', '1', "0011000000111001"), -- 18
|
||||||
|
("0011000000111001", '1', '1', '1', "0000000000000000"), -- 19
|
||||||
|
("0011000000111001", '0', '0', '1', "0000000000000000"), -- 20
|
||||||
|
("0011000000111001", '0', '0', '1', "0000000000000001"), -- 21
|
||||||
|
|
||||||
|
("0011000000111001", '1', '0', '1', "0000000000000010"), -- 22 (revised)
|
||||||
|
-- ("0011000000111001", '1', '0', '1', "0000000000000001"), -- 22 (here)
|
||||||
|
|
||||||
|
("0011000000111001", '1', '0', '1', "0000000000000000"), -- 23
|
||||||
|
("0000000000000000", '0', '1', '1', "0000000000000000"), -- 24
|
||||||
|
("0000000000000000", '0', '1', '1', "0000000000000000"), -- 25
|
||||||
|
("0000000000000000", '0', '0', '1', "0000000000000000"), -- 26
|
||||||
|
("0000000000000000", '0', '0', '1', "0000000000000001"), -- 27
|
||||||
|
|
||||||
|
("0101011011001110", '1', '0', '0', "0000000000000010"), -- 28 (revised)
|
||||||
|
-- ("0101011011001110", '1', '0', '0', "0000000000000001"), -- 28 (here)
|
||||||
|
|
||||||
|
("0101011011001110", '1', '0', '0', "0000000000000000"), -- 29
|
||||||
|
|
||||||
|
("0000000000000000", '1', '0', '0', "0000000000000000"), -- 30
|
||||||
|
("0000000000000000", '0', '0', '1', "0000000000000000"), -- 31
|
||||||
|
("0000000000000000", '0', '0', '1', "0000000000000001"), -- 32
|
||||||
|
("0000000000000000", '0', '0', '1', "0000000000000010"), -- 33
|
||||||
|
("0000000000000000", '0', '0', '1', "0000000000000011"), -- 34
|
||||||
|
("0000000000000000", '0', '0', '1', "0000000000000100"), -- 35
|
||||||
|
("0000000000000000", '0', '0', '1', "0000000000000101") -- 36
|
||||||
|
);
|
||||||
|
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
d <= patterns(i).d;
|
||||||
|
reset <= patterns(i).reset;
|
||||||
|
load <= patterns(i).load;
|
||||||
|
inc <= patterns(i).inc;
|
||||||
|
wait for 0.25 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad counter" severity error;
|
||||||
|
wait for 0.75 ns;
|
||||||
|
end loop;
|
||||||
|
-- End the clock
|
||||||
|
finish <= '1';
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end pc_tb_arch;
|
40
src/ram16k.vhdl
Normal file
40
src/ram16k.vhdl
Normal file
@ -0,0 +1,40 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity ram16k is
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(14 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end ram16k;
|
||||||
|
|
||||||
|
architecture ram16k_arch of ram16k is
|
||||||
|
component ram4k
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(11 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
component dmux8way
|
||||||
|
port (cin : in std_logic; sel : in std_logic_vector(2 downto 0); a, b, c, d, e, f, g, h : out std_logic);
|
||||||
|
end component;
|
||||||
|
component mux8way16
|
||||||
|
port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(2 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal ramLoad : std_logic_vector(7 downto 0);
|
||||||
|
type ramoutT is array (7 downto 0) of std_logic_vector(15 downto 0);
|
||||||
|
signal ramOut : ramoutT;
|
||||||
|
begin
|
||||||
|
dmux8way_0: dmux8way port map (load, address(2 downto 0), ramLoad(0), ramLoad(1), ramLoad(2), ramLoad(3), ramLoad(4), ramLoad(5), ramLoad(6), ramLoad(7));
|
||||||
|
|
||||||
|
ram: for i in ramLoad'range generate
|
||||||
|
ram4k_i: ram4k port map (d, ramLoad(i), address(14 downto 3), clk, ramOut(i));
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
mux8way16_0: mux8way16 port map (ramOut(0), ramOut(1), ramOut(2), ramOut(3), ramOut(4), ramOut(5), ramOut(6), ramOut(7), address(2 downto 0), cout);
|
||||||
|
end ram16k_arch;
|
385
src/ram16k_tb.vhdl
Normal file
385
src/ram16k_tb.vhdl
Normal file
@ -0,0 +1,385 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity ram16k_tb is
|
||||||
|
end ram16k_tb;
|
||||||
|
|
||||||
|
architecture ram16k_tb_arch of ram16k_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component ram16k
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(14 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Declaration of the clock
|
||||||
|
component Clock
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for ram16k_0: ram16k use entity work.ram16k;
|
||||||
|
signal d, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal address : std_logic_vector(14 downto 0);
|
||||||
|
signal load, finish, clk : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
OSC_CLK: Clock port map (finish, clk);
|
||||||
|
ram16k_0: ram16k port map (d, load, address, clk, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the ram16k.
|
||||||
|
d : std_logic_vector(15 downto 0);
|
||||||
|
load : std_logic;
|
||||||
|
address : std_logic_vector(14 downto 0);
|
||||||
|
-- The output of the ram16k.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", '0', "000000000000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '0', "000000000000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "000000000000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "000000000000000", "0000000000000000"),
|
||||||
|
("0001000011100001", '0', "000000000000000", "0000000000000000"),
|
||||||
|
("0001000011100001", '0', "000000000000000", "0000000000000000"),
|
||||||
|
("0001000011100001", '1', "001000011100001", "0000000000000000"),
|
||||||
|
("0001000011100001", '1', "001000011100001", "0001000011100001"),
|
||||||
|
("0001000011100001", '0', "000000000000000", "0000000000000000"),
|
||||||
|
("0001000011100001", '0', "000000000000000", "0000000000000000"),
|
||||||
|
("0011000000111001", '0', "011000000111001", "0000000000000000"),
|
||||||
|
("0011000000111001", '0', "011000000111001", "0000000000000000"),
|
||||||
|
("0011000000111001", '1', "011000000111001", "0000000000000000"),
|
||||||
|
("0011000000111001", '1', "011000000111001", "0011000000111001"),
|
||||||
|
("0011000000111001", '0', "011000000111001", "0011000000111001"),
|
||||||
|
("0011000000111001", '0', "011000000111001", "0011000000111001"),
|
||||||
|
("0011000000111001", '0', "001000011100001", "0001000011100001"),
|
||||||
|
("0011111111111111", '0', "001000011100001", "0001000011100001"),
|
||||||
|
("0011111111111111", '0', "001000011100001", "0001000011100001"),
|
||||||
|
("0011111111111111", '1', "011111111111111", "0000000000000000"),
|
||||||
|
("0011111111111111", '1', "011111111111111", "0011111111111111"),
|
||||||
|
("0011111111111111", '0', "011111111111111", "0011111111111111"),
|
||||||
|
("0011111111111111", '0', "011111111111111", "0011111111111111"),
|
||||||
|
("0011111111111111", '0', "011000000111001", "0011000000111001"),
|
||||||
|
("0011111111111111", '0', "011111111111111", "0011111111111111"),
|
||||||
|
("0011111111111111", '0', "010101010101000", "0000000000000000"),
|
||||||
|
("0011111111111111", '0', "010101010101000", "0000000000000000"),
|
||||||
|
("0011111111111111", '0', "010101010101001", "0000000000000000"),
|
||||||
|
("0011111111111111", '0', "010101010101010", "0000000000000000"),
|
||||||
|
("0011111111111111", '0', "010101010101011", "0000000000000000"),
|
||||||
|
("0011111111111111", '0', "010101010101100", "0000000000000000"),
|
||||||
|
("0011111111111111", '0', "010101010101101", "0000000000000000"),
|
||||||
|
("0011111111111111", '0', "010101010101110", "0000000000000000"),
|
||||||
|
("0011111111111111", '0', "010101010101111", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101010101000", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101001", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101011", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101100", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101110", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101111", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101000", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101001", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101001", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101001", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101011", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101011", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101011", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101100", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101100", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101100", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101110", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101110", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010101110", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010101111", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010101111", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010101111", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101001", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101011", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101100", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101110", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000010101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "000010101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "000110101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "001010101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "001110101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "010010101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "010110101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "011010101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "011110101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "000010101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "000110101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "001010101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "001110101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010010101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010110101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "011010101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "011110101010101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "000010101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "000010101010101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "000110101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000110101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "000110101010101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "001010101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001010101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "001010101010101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "001110101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001110101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "001110101010101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010010101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010010101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010010101010101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010110101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010110101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010110101010101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "011010101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011010101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "011010101010101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "011110101010101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011110101010101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "011110101010101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "011110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "001010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "001110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011110101010101", "0101010101010101"));
|
||||||
|
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
d <= patterns(i).d;
|
||||||
|
load <= patterns(i).load;
|
||||||
|
address <= patterns(i).address;
|
||||||
|
wait for 0.25 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad data, memory problem" severity error;
|
||||||
|
wait for 0.75 ns;
|
||||||
|
end loop;
|
||||||
|
-- End the clock
|
||||||
|
finish <= '1';
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end ram16k_tb_arch;
|
40
src/ram4k.vhdl
Normal file
40
src/ram4k.vhdl
Normal file
@ -0,0 +1,40 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity ram4k is
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(11 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end ram4k;
|
||||||
|
|
||||||
|
architecture ram4k_arch of ram4k is
|
||||||
|
component ram512
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(8 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
component dmux8way
|
||||||
|
port (cin : in std_logic; sel : in std_logic_vector(2 downto 0); a, b, c, d, e, f, g, h : out std_logic);
|
||||||
|
end component;
|
||||||
|
component mux8way16
|
||||||
|
port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(2 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal ramLoad : std_logic_vector(7 downto 0);
|
||||||
|
type ramoutT is array (7 downto 0) of std_logic_vector(15 downto 0);
|
||||||
|
signal ramOut : ramoutT;
|
||||||
|
begin
|
||||||
|
dmux8way_0: dmux8way port map (load, address(2 downto 0), ramLoad(0), ramLoad(1), ramLoad(2), ramLoad(3), ramLoad(4), ramLoad(5), ramLoad(6), ramLoad(7));
|
||||||
|
|
||||||
|
ram: for i in ramLoad'range generate
|
||||||
|
ram512_i: ram512 port map (d, ramLoad(i), address(11 downto 3), clk, ramOut(i));
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
mux8way16_0: mux8way16 port map (ramOut(0), ramOut(1), ramOut(2), ramOut(3), ramOut(4), ramOut(5), ramOut(6), ramOut(7), address(2 downto 0), cout);
|
||||||
|
end ram4k_arch;
|
385
src/ram4k_tb.vhdl
Normal file
385
src/ram4k_tb.vhdl
Normal file
@ -0,0 +1,385 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity ram4k_tb is
|
||||||
|
end ram4k_tb;
|
||||||
|
|
||||||
|
architecture ram4k_tb_arch of ram4k_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component ram4k
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(11 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Declaration of the clock
|
||||||
|
component Clock
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for ram4k_0: ram4k use entity work.ram4k;
|
||||||
|
signal d, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal address : std_logic_vector(11 downto 0);
|
||||||
|
signal load, finish, clk : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
OSC_CLK: Clock port map (finish, clk);
|
||||||
|
ram4k_0: ram4k port map (d, load, address, clk, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the ram4k.
|
||||||
|
d : std_logic_vector(15 downto 0);
|
||||||
|
load : std_logic;
|
||||||
|
address : std_logic_vector(11 downto 0);
|
||||||
|
-- The output of the ram4k.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", '0', "000000000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '0', "000000000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "000000000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "000000000000", "0000000000000000"),
|
||||||
|
("0000010001010111", '0', "000000000000", "0000000000000000"),
|
||||||
|
("0000010001010111", '0', "000000000000", "0000000000000000"),
|
||||||
|
("0000010001010111", '1', "010001010111", "0000000000000000"),
|
||||||
|
("0000010001010111", '1', "010001010111", "0000010001010111"),
|
||||||
|
("0000010001010111", '0', "000000000000", "0000000000000000"),
|
||||||
|
("0000010001010111", '0', "000000000000", "0000000000000000"),
|
||||||
|
("0000110110111001", '0', "110110111001", "0000000000000000"),
|
||||||
|
("0000110110111001", '0', "110110111001", "0000000000000000"),
|
||||||
|
("0000110110111001", '1', "110110111001", "0000000000000000"),
|
||||||
|
("0000110110111001", '1', "110110111001", "0000110110111001"),
|
||||||
|
("0000110110111001", '0', "110110111001", "0000110110111001"),
|
||||||
|
("0000110110111001", '0', "110110111001", "0000110110111001"),
|
||||||
|
("0000110110111001", '0', "010001010111", "0000010001010111"),
|
||||||
|
("0000111111111111", '0', "010001010111", "0000010001010111"),
|
||||||
|
("0000111111111111", '0', "010001010111", "0000010001010111"),
|
||||||
|
("0000111111111111", '1', "111111111111", "0000000000000000"),
|
||||||
|
("0000111111111111", '1', "111111111111", "0000111111111111"),
|
||||||
|
("0000111111111111", '0', "111111111111", "0000111111111111"),
|
||||||
|
("0000111111111111", '0', "111111111111", "0000111111111111"),
|
||||||
|
("0000111111111111", '0', "110110111001", "0000110110111001"),
|
||||||
|
("0000111111111111", '0', "111111111111", "0000111111111111"),
|
||||||
|
("0000111111111111", '0', "101010101000", "0000000000000000"),
|
||||||
|
("0000111111111111", '0', "101010101000", "0000000000000000"),
|
||||||
|
("0000111111111111", '0', "101010101001", "0000000000000000"),
|
||||||
|
("0000111111111111", '0', "101010101010", "0000000000000000"),
|
||||||
|
("0000111111111111", '0', "101010101011", "0000000000000000"),
|
||||||
|
("0000111111111111", '0', "101010101100", "0000000000000000"),
|
||||||
|
("0000111111111111", '0', "101010101101", "0000000000000000"),
|
||||||
|
("0000111111111111", '0', "101010101110", "0000000000000000"),
|
||||||
|
("0000111111111111", '0', "101010101111", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101010101000", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101010101001", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101010101001", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101010101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101010101011", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101010101011", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101010101100", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101010101100", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101010101101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101010101101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101010101110", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101010101110", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101010101111", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101010101001", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101010101011", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101010101100", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101010101101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101010101110", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101010101111", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "101010101000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "101010101000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "101010101000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101010101000", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "101010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "101010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "101010101001", "0101010101010110"),
|
||||||
|
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||||||
|
("0101010101010101", '0', "001101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "100101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "110101010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "111101010101", "0101010101010101"));
|
||||||
|
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
d <= patterns(i).d;
|
||||||
|
load <= patterns(i).load;
|
||||||
|
address <= patterns(i).address;
|
||||||
|
wait for 0.25 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad data, memory problem" severity error;
|
||||||
|
wait for 0.75 ns;
|
||||||
|
end loop;
|
||||||
|
-- End the clock
|
||||||
|
finish <= '1';
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end ram4k_tb_arch;
|
40
src/ram512.vhdl
Normal file
40
src/ram512.vhdl
Normal file
@ -0,0 +1,40 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity ram512 is
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(8 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end ram512;
|
||||||
|
|
||||||
|
architecture ram512_arch of ram512 is
|
||||||
|
component ram64
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(5 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
component dmux8way
|
||||||
|
port (cin : in std_logic; sel : in std_logic_vector(2 downto 0); a, b, c, d, e, f, g, h : out std_logic);
|
||||||
|
end component;
|
||||||
|
component mux8way16
|
||||||
|
port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(2 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal ramLoad : std_logic_vector(7 downto 0);
|
||||||
|
type ramoutT is array (7 downto 0) of std_logic_vector(15 downto 0);
|
||||||
|
signal ramOut : ramoutT;
|
||||||
|
begin
|
||||||
|
dmux8way_0: dmux8way port map (load, address(2 downto 0), ramLoad(0), ramLoad(1), ramLoad(2), ramLoad(3), ramLoad(4), ramLoad(5), ramLoad(6), ramLoad(7));
|
||||||
|
|
||||||
|
ram: for i in ramLoad'range generate
|
||||||
|
ram64_i: ram64 port map (d, ramLoad(i), address(8 downto 3), clk, ramOut(i));
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
mux8way16_0: mux8way16 port map (ramOut(0), ramOut(1), ramOut(2), ramOut(3), ramOut(4), ramOut(5), ramOut(6), ramOut(7), address(2 downto 0), cout);
|
||||||
|
end ram512_arch;
|
385
src/ram512_tb.vhdl
Normal file
385
src/ram512_tb.vhdl
Normal file
@ -0,0 +1,385 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity ram512_tb is
|
||||||
|
end ram512_tb;
|
||||||
|
|
||||||
|
architecture ram512_tb_arch of ram512_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component ram512
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(8 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Declaration of the clock
|
||||||
|
component Clock
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for ram512_0: ram512 use entity work.ram512;
|
||||||
|
signal d, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal address : std_logic_vector(8 downto 0);
|
||||||
|
signal load, finish, clk : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
OSC_CLK: Clock port map (finish, clk);
|
||||||
|
ram512_0: ram512 port map (d, load, address, clk, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the ram512.
|
||||||
|
d : std_logic_vector(15 downto 0);
|
||||||
|
load : std_logic;
|
||||||
|
address : std_logic_vector(8 downto 0);
|
||||||
|
-- The output of the ram512.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", '0', "000000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '0', "000000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "000000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "000000000", "0000000000000000"),
|
||||||
|
("0011001100101011", '0', "000000000", "0000000000000000"),
|
||||||
|
("0011001100101011", '0', "000000000", "0000000000000000"),
|
||||||
|
("0011001100101011", '1', "010000010", "0000000000000000"),
|
||||||
|
("0011001100101011", '1', "010000010", "0011001100101011"),
|
||||||
|
("0011001100101011", '0', "000000000", "0000000000000000"),
|
||||||
|
("0011001100101011", '0', "000000000", "0000000000000000"),
|
||||||
|
("0001001001111001", '0', "111011000", "0000000000000000"),
|
||||||
|
("0001001001111001", '0', "111011000", "0000000000000000"),
|
||||||
|
("0001001001111001", '1', "111011000", "0000000000000000"),
|
||||||
|
("0001001001111001", '1', "111011000", "0001001001111001"),
|
||||||
|
("0001001001111001", '0', "111011000", "0001001001111001"),
|
||||||
|
("0001001001111001", '0', "111011000", "0001001001111001"),
|
||||||
|
("0001001001111001", '0', "010000010", "0011001100101011"),
|
||||||
|
("0001001111111111", '0', "010000010", "0011001100101011"),
|
||||||
|
("0001001111111111", '0', "010000010", "0011001100101011"),
|
||||||
|
("0001001111111111", '1', "111111111", "0000000000000000"),
|
||||||
|
("0001001111111111", '1', "111111111", "0001001111111111"),
|
||||||
|
("0001001111111111", '0', "111111111", "0001001111111111"),
|
||||||
|
("0001001111111111", '0', "111111111", "0001001111111111"),
|
||||||
|
("0001001111111111", '0', "111011000", "0001001001111001"),
|
||||||
|
("0001001111111111", '0', "111111111", "0001001111111111"),
|
||||||
|
("0001001111111111", '0', "010101000", "0000000000000000"),
|
||||||
|
("0001001111111111", '0', "010101000", "0000000000000000"),
|
||||||
|
("0001001111111111", '0', "010101001", "0000000000000000"),
|
||||||
|
("0001001111111111", '0', "010101010", "0000000000000000"),
|
||||||
|
("0001001111111111", '0', "010101011", "0000000000000000"),
|
||||||
|
("0001001111111111", '0', "010101100", "0000000000000000"),
|
||||||
|
("0001001111111111", '0', "010101101", "0000000000000000"),
|
||||||
|
("0001001111111111", '0', "010101110", "0000000000000000"),
|
||||||
|
("0001001111111111", '0', "010101111", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101000", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101001", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101011", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101100", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101110", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101111", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101000", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101001", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101001", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101001", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101011", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101011", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101011", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101100", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101100", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101100", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101110", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101110", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101110", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101111", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101111", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101111", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101001", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101011", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101100", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101110", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101111", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "000101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "001101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "100101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "101101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "110101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '0', "111101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "000101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "001101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "011101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "100101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "110101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "111101010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "000101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "000101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "001101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "001101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "011101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "011101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "100101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "100101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "101101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "110101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "110101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "111101010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "111101010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "111101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "001101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "100101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "110101010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "111101010", "0101010101010101"));
|
||||||
|
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
d <= patterns(i).d;
|
||||||
|
load <= patterns(i).load;
|
||||||
|
address <= patterns(i).address;
|
||||||
|
wait for 0.25 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad data, memory problem" severity error;
|
||||||
|
wait for 0.75 ns;
|
||||||
|
end loop;
|
||||||
|
-- End the clock
|
||||||
|
finish <= '1';
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end ram512_tb_arch;
|
40
src/ram64.vhdl
Normal file
40
src/ram64.vhdl
Normal file
@ -0,0 +1,40 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity ram64 is
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(5 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end ram64;
|
||||||
|
|
||||||
|
architecture ram64_arch of ram64 is
|
||||||
|
component ram8
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(2 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
component dmux8way
|
||||||
|
port (cin : in std_logic; sel : in std_logic_vector(2 downto 0); a, b, c, d, e, f, g, h : out std_logic);
|
||||||
|
end component;
|
||||||
|
component mux8way16
|
||||||
|
port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(2 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal ramLoad : std_logic_vector(7 downto 0);
|
||||||
|
type ramoutT is array (7 downto 0) of std_logic_vector(15 downto 0);
|
||||||
|
signal ramOut : ramoutT;
|
||||||
|
begin
|
||||||
|
dmux8way_0: dmux8way port map (load, address(2 downto 0), ramLoad(0), ramLoad(1), ramLoad(2), ramLoad(3), ramLoad(4), ramLoad(5), ramLoad(6), ramLoad(7));
|
||||||
|
|
||||||
|
ram: for i in ramLoad'range generate
|
||||||
|
ram8_i: ram8 port map (d, ramLoad(i), address(5 downto 3), clk, ramOut(i));
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
mux8way16_0: mux8way16 port map (ramOut(0), ramOut(1), ramOut(2), ramOut(3), ramOut(4), ramOut(5), ramOut(6), ramOut(7), address(2 downto 0), cout);
|
||||||
|
end ram64_arch;
|
385
src/ram64_tb.vhdl
Normal file
385
src/ram64_tb.vhdl
Normal file
@ -0,0 +1,385 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity ram64_tb is
|
||||||
|
end ram64_tb;
|
||||||
|
|
||||||
|
architecture ram64_tb_arch of ram64_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component ram64
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(5 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Declaration of the clock
|
||||||
|
component Clock
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for ram64_0: ram64 use entity work.ram64;
|
||||||
|
signal d, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal address : std_logic_vector(5 downto 0);
|
||||||
|
signal load, finish, clk : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
OSC_CLK: Clock port map (finish, clk);
|
||||||
|
ram64_0: ram64 port map (d, load, address, clk, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the ram64.
|
||||||
|
d : std_logic_vector(15 downto 0);
|
||||||
|
load : std_logic;
|
||||||
|
address : std_logic_vector(5 downto 0);
|
||||||
|
-- The output of the ram64.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", '0', "000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '0', "000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "000000", "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "000000", "0000000000000000"),
|
||||||
|
("0000010100100001", '0', "000000", "0000000000000000"),
|
||||||
|
("0000010100100001", '0', "000000", "0000000000000000"),
|
||||||
|
("0000010100100001", '1', "001101", "0000000000000000"),
|
||||||
|
("0000010100100001", '1', "001101", "0000010100100001"),
|
||||||
|
("0000010100100001", '0', "000000", "0000000000000000"),
|
||||||
|
("0000010100100001", '0', "000000", "0000000000000000"),
|
||||||
|
("0001001010001011", '0', "101111", "0000000000000000"),
|
||||||
|
("0001001010001011", '0', "101111", "0000000000000000"),
|
||||||
|
("0001001010001011", '1', "101111", "0000000000000000"),
|
||||||
|
("0001001010001011", '1', "101111", "0001001010001011"),
|
||||||
|
("0001001010001011", '0', "101111", "0001001010001011"),
|
||||||
|
("0001001010001011", '0', "101111", "0001001010001011"),
|
||||||
|
("0001001010001011", '0', "001101", "0000010100100001"),
|
||||||
|
("0001100011011011", '0', "001101", "0000010100100001"),
|
||||||
|
("0001100011011011", '0', "001101", "0000010100100001"),
|
||||||
|
("0001100011011011", '1', "111111", "0000000000000000"),
|
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||||||
|
("0101010101010101", '1', "100101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "101101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "110101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "110101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "110101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "111101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "110101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "110101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "111101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "111101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "111101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "111101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "001101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "100101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "110101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "111101", "0101010101010101"));
|
||||||
|
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
d <= patterns(i).d;
|
||||||
|
load <= patterns(i).load;
|
||||||
|
address <= patterns(i).address;
|
||||||
|
wait for 0.25 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad data, memory problem" severity error;
|
||||||
|
wait for 0.75 ns;
|
||||||
|
end loop;
|
||||||
|
-- End the clock
|
||||||
|
finish <= '1';
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end ram64_tb_arch;
|
38
src/ram8.vhdl
Normal file
38
src/ram8.vhdl
Normal file
@ -0,0 +1,38 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
entity ram8 is
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(2 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end ram8;
|
||||||
|
|
||||||
|
architecture ram8_arch of ram8 is
|
||||||
|
component dregister
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load, clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
component dmux8way
|
||||||
|
port (cin : in std_logic; sel : in std_logic_vector(2 downto 0); a, b, c, d, e, f, g, h : out std_logic);
|
||||||
|
end component;
|
||||||
|
component mux8way16
|
||||||
|
port (a, b, c, d, e, f, g, h : in std_logic_vector(15 downto 0);
|
||||||
|
sel : in std_logic_vector(2 downto 0);
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
|
||||||
|
signal regLoad : std_logic_vector(7 downto 0);
|
||||||
|
type regoutT is array (7 downto 0) of std_logic_vector(15 downto 0);
|
||||||
|
signal regOut : regoutT;
|
||||||
|
begin
|
||||||
|
dmux8way_0: dmux8way port map (load, address, regLoad(0), regLoad(1), regLoad(2), regLoad(3), regLoad(4), regLoad(5), regLoad(6), regLoad(7));
|
||||||
|
|
||||||
|
reg: for i in regLoad'range generate
|
||||||
|
dregister_i: dregister port map (d, regLoad(i), clk, regOut(i));
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
mux8way16_0: mux8way16 port map (regOut(0), regOut(1), regOut(2), regOut(3), regOut(4), regOut(5), regOut(6), regOut(7), address, cout);
|
||||||
|
end ram8_arch;
|
238
src/ram8_tb.vhdl
Normal file
238
src/ram8_tb.vhdl
Normal file
@ -0,0 +1,238 @@
|
|||||||
|
library IEEE;
|
||||||
|
use IEEE.std_logic_1164.all;
|
||||||
|
|
||||||
|
-- A testbench has no ports.
|
||||||
|
entity ram8_tb is
|
||||||
|
end ram8_tb;
|
||||||
|
|
||||||
|
architecture ram8_tb_arch of ram8_tb is
|
||||||
|
-- Declaration of the component that will be instantiated.
|
||||||
|
component ram8
|
||||||
|
port (d : in std_logic_vector(15 downto 0);
|
||||||
|
load : in std_logic;
|
||||||
|
address : in std_logic_vector(2 downto 0);
|
||||||
|
clk : in std_logic;
|
||||||
|
cout : out std_logic_vector(15 downto 0));
|
||||||
|
end component;
|
||||||
|
-- Declaration of the clock
|
||||||
|
component Clock
|
||||||
|
port (finish : in std_logic;
|
||||||
|
cout : out std_logic);
|
||||||
|
end component;
|
||||||
|
|
||||||
|
-- Specifies which entity is bound with the component.
|
||||||
|
for ram8_0: ram8 use entity work.ram8;
|
||||||
|
signal d, cout : std_logic_vector(15 downto 0);
|
||||||
|
signal address : std_logic_vector(2 downto 0);
|
||||||
|
signal load, finish, clk : std_logic;
|
||||||
|
begin
|
||||||
|
-- Component instantiation.
|
||||||
|
OSC_CLK: Clock port map (finish, clk);
|
||||||
|
ram8_0: ram8 port map (d, load, address, clk, cout);
|
||||||
|
|
||||||
|
-- This process does the real job.
|
||||||
|
process
|
||||||
|
type pattern_type is record
|
||||||
|
-- The inputs of the ram8.
|
||||||
|
d : std_logic_vector(15 downto 0);
|
||||||
|
load : std_logic;
|
||||||
|
address : std_logic_vector(2 downto 0);
|
||||||
|
-- The output of the ram8.
|
||||||
|
cout : std_logic_vector(15 downto 0);
|
||||||
|
end record;
|
||||||
|
-- The patterns to apply.
|
||||||
|
type pattern_array is array (natural range <>) of pattern_type;
|
||||||
|
constant patterns : pattern_array :=
|
||||||
|
(("0000000000000000", '0', "000", "0000000000000000"),
|
||||||
|
("0000000000000000", '0', "000", "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "000", "0000000000000000"),
|
||||||
|
("0000000000000000", '1', "000", "0000000000000000"),
|
||||||
|
("0010101101100111", '0', "000", "0000000000000000"),
|
||||||
|
("0010101101100111", '0', "000", "0000000000000000"),
|
||||||
|
("0010101101100111", '1', "001", "0000000000000000"),
|
||||||
|
("0010101101100111", '1', "001", "0010101101100111"),
|
||||||
|
("0010101101100111", '0', "000", "0000000000000000"),
|
||||||
|
("0010101101100111", '0', "000", "0000000000000000"),
|
||||||
|
("0000110100000101", '0', "011", "0000000000000000"),
|
||||||
|
("0000110100000101", '0', "011", "0000000000000000"),
|
||||||
|
("0000110100000101", '1', "011", "0000000000000000"),
|
||||||
|
("0000110100000101", '1', "011", "0000110100000101"),
|
||||||
|
("0000110100000101", '0', "011", "0000110100000101"),
|
||||||
|
("0000110100000101", '0', "011", "0000110100000101"),
|
||||||
|
("0000110100000101", '0', "001", "0010101101100111"),
|
||||||
|
("0001111001100001", '0', "001", "0010101101100111"),
|
||||||
|
("0001111001100001", '0', "001", "0010101101100111"),
|
||||||
|
("0001111001100001", '1', "111", "0000000000000000"),
|
||||||
|
("0001111001100001", '1', "111", "0001111001100001"),
|
||||||
|
("0001111001100001", '0', "111", "0001111001100001"),
|
||||||
|
("0001111001100001", '0', "111", "0001111001100001"),
|
||||||
|
("0001111001100001", '0', "011", "0000110100000101"),
|
||||||
|
("0001111001100001", '0', "111", "0001111001100001"),
|
||||||
|
("0001111001100001", '0', "000", "0000000000000000"),
|
||||||
|
("0001111001100001", '0', "000", "0000000000000000"),
|
||||||
|
("0001111001100001", '0', "001", "0010101101100111"),
|
||||||
|
("0001111001100001", '0', "010", "0000000000000000"),
|
||||||
|
("0001111001100001", '0', "011", "0000110100000101"),
|
||||||
|
("0001111001100001", '0', "100", "0000000000000000"),
|
||||||
|
("0001111001100001", '0', "101", "0000000000000000"),
|
||||||
|
("0001111001100001", '0', "110", "0000000000000000"),
|
||||||
|
("0001111001100001", '0', "111", "0001111001100001"),
|
||||||
|
("0101010101010101", '1', "000", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "000", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "001", "0010101101100111"),
|
||||||
|
("0101010101010101", '1', "001", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "010", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "011", "0000110100000101"),
|
||||||
|
("0101010101010101", '1', "011", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "100", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "100", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "101", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "110", "0000000000000000"),
|
||||||
|
("0101010101010101", '1', "110", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "111", "0001111001100001"),
|
||||||
|
("0101010101010101", '1', "111", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "001", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "100", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "110", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "111", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "000", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "001", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "001", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "001", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "001", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "010", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "010", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "011", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "011", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "011", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "011", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "100", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "100", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "100", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "100", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "101", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "101", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "110", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "110", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "111", "0101010101010101"),
|
||||||
|
("0101010101010101", '1', "110", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "110", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "111", "0101010101010101"),
|
||||||
|
("0101010101010110", '1', "111", "0101010101010110"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "001", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "010", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "011", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "100", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "101", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "110", "0101010101010101"),
|
||||||
|
("0101010101010110", '0', "111", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "111", "0101010101010110"),
|
||||||
|
("0101010101010101", '1', "111", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "000", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "001", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "010", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "011", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "100", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "101", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "110", "0101010101010101"),
|
||||||
|
("0101010101010101", '0', "111", "0101010101010101"));
|
||||||
|
|
||||||
|
begin
|
||||||
|
-- Check each pattern.
|
||||||
|
for i in patterns'range loop
|
||||||
|
-- Set the inputs.
|
||||||
|
d <= patterns(i).d;
|
||||||
|
load <= patterns(i).load;
|
||||||
|
address <= patterns(i).address;
|
||||||
|
wait for 0.25 ns;
|
||||||
|
-- Check the outputs.
|
||||||
|
assert cout = patterns(i).cout
|
||||||
|
report "bad data, memory problem" severity error;
|
||||||
|
wait for 0.75 ns;
|
||||||
|
end loop;
|
||||||
|
-- End the clock
|
||||||
|
finish <= '1';
|
||||||
|
assert false report "end of test" severity note;
|
||||||
|
-- Wait forever; this will finish the simulation.
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
end ram8_tb_arch;
|
27
src/wave/gtkw/add16.gtkw
Normal file
27
src/wave/gtkw/add16.gtkw
Normal file
@ -0,0 +1,27 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Tue May 19 00:54:23 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/add16.vcd"
|
||||||
|
[dumpfile_mtime] "Tue May 19 00:46:45 2015"
|
||||||
|
[dumpfile_size] 6415
|
||||||
|
[savefile] "/home/collin/hack/src/wave/add16.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*0.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 110
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@22
|
||||||
|
a[15:0]
|
||||||
|
b[15:0]
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@23
|
||||||
|
cout[15:0]
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
33
src/wave/gtkw/adder.gtkw
Normal file
33
src/wave/gtkw/adder.gtkw
Normal file
@ -0,0 +1,33 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Tue May 19 00:54:03 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/adder.vcd"
|
||||||
|
[dumpfile_mtime] "Tue May 19 00:46:45 2015"
|
||||||
|
[dumpfile_size] 570
|
||||||
|
[savefile] "/home/collin/hack/src/wave/adder.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-19.992342 125000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 97
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@28
|
||||||
|
a
|
||||||
|
b
|
||||||
|
ci
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@800201
|
||||||
|
-out
|
||||||
|
@29
|
||||||
|
co
|
||||||
|
s
|
||||||
|
@1000201
|
||||||
|
-out
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
49
src/wave/gtkw/alu.gtkw
Normal file
49
src/wave/gtkw/alu.gtkw
Normal file
@ -0,0 +1,49 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Tue May 19 01:35:58 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/alu.vcd"
|
||||||
|
[dumpfile_mtime] "Tue May 19 01:04:56 2015"
|
||||||
|
[dumpfile_size] 32724
|
||||||
|
[savefile] "/home/collin/hack/src/wave/alu.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-22.222769 730000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 156
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@22
|
||||||
|
x[15:0]
|
||||||
|
y[15:0]
|
||||||
|
@29
|
||||||
|
[color] 7
|
||||||
|
zx
|
||||||
|
[color] 7
|
||||||
|
nx
|
||||||
|
[color] 7
|
||||||
|
zy
|
||||||
|
[color] 7
|
||||||
|
ny
|
||||||
|
[color] 7
|
||||||
|
no
|
||||||
|
[color] 7
|
||||||
|
f
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@800200
|
||||||
|
-out
|
||||||
|
@22
|
||||||
|
cout[15:0]
|
||||||
|
@28
|
||||||
|
[color] 5
|
||||||
|
zr
|
||||||
|
[color] 5
|
||||||
|
ng
|
||||||
|
@1000200
|
||||||
|
-out
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
27
src/wave/gtkw/dff.gtkw
Normal file
27
src/wave/gtkw/dff.gtkw
Normal file
@ -0,0 +1,27 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Wed May 20 20:16:50 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/dff.vcd"
|
||||||
|
[dumpfile_mtime] "Wed May 20 08:44:58 2015"
|
||||||
|
[dumpfile_size] 894
|
||||||
|
[savefile] "/home/collin/hack/src/wave/dff.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-20.698320 170000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 78
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@28
|
||||||
|
clk
|
||||||
|
d
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@28
|
||||||
|
cout
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
33
src/wave/gtkw/dmux.gtkw
Normal file
33
src/wave/gtkw/dmux.gtkw
Normal file
@ -0,0 +1,33 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Wed May 20 05:22:42 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/dmux.vcd"
|
||||||
|
[dumpfile_mtime] "Wed May 20 05:21:34 2015"
|
||||||
|
[dumpfile_size] 463
|
||||||
|
[savefile] "/home/collin/hack/src/wave/dmux.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-18.992342 2114000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 96
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@28
|
||||||
|
cin
|
||||||
|
@29
|
||||||
|
sel
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@800200
|
||||||
|
-out
|
||||||
|
@28
|
||||||
|
a
|
||||||
|
b
|
||||||
|
@1000200
|
||||||
|
-out
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
35
src/wave/gtkw/dmux4way.gtkw
Normal file
35
src/wave/gtkw/dmux4way.gtkw
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Wed May 20 06:14:19 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/dmux4way.vcd"
|
||||||
|
[dumpfile_mtime] "Wed May 20 06:13:23 2015"
|
||||||
|
[dumpfile_size] 1226
|
||||||
|
[savefile] "/home/collin/hack/src/wave/dmux4way.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-20.045994 7000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[treeopen] dmux4way_0.
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 134
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@28
|
||||||
|
dmux4way_0.cin
|
||||||
|
dmux4way_0.sel[1:0]
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@800201
|
||||||
|
-out
|
||||||
|
@29
|
||||||
|
dmux4way_0.a
|
||||||
|
dmux4way_0.b
|
||||||
|
dmux4way_0.c
|
||||||
|
dmux4way_0.d
|
||||||
|
@1000201
|
||||||
|
-out
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
38
src/wave/gtkw/dmux8way.gtkw
Normal file
38
src/wave/gtkw/dmux8way.gtkw
Normal file
@ -0,0 +1,38 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Wed May 20 06:26:27 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/dmux8way.vcd"
|
||||||
|
[dumpfile_mtime] "Wed May 20 06:25:26 2015"
|
||||||
|
[dumpfile_size] 3246
|
||||||
|
[savefile] "/home/collin/hack/src/wave/dmux8way.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-21.007469 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 94
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800201
|
||||||
|
-in
|
||||||
|
@29
|
||||||
|
cin
|
||||||
|
sel[2:0]
|
||||||
|
@1000201
|
||||||
|
-in
|
||||||
|
@800200
|
||||||
|
-out
|
||||||
|
@28
|
||||||
|
a
|
||||||
|
b
|
||||||
|
c
|
||||||
|
d
|
||||||
|
e
|
||||||
|
f
|
||||||
|
g
|
||||||
|
h
|
||||||
|
@1000200
|
||||||
|
-out
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
30
src/wave/gtkw/dregister.gtkw
Normal file
30
src/wave/gtkw/dregister.gtkw
Normal file
@ -0,0 +1,30 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Wed May 20 08:56:20 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/dregister.vcd"
|
||||||
|
[dumpfile_mtime] "Wed May 20 08:43:27 2015"
|
||||||
|
[dumpfile_size] 67014
|
||||||
|
[savefile] "/home/collin/hack/src/wave/dregister.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-24.288025 41000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 167
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@28
|
||||||
|
clk
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@23
|
||||||
|
d[15:0]
|
||||||
|
@28
|
||||||
|
load
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@22
|
||||||
|
cout[15:0]
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
28
src/wave/gtkw/mux.gtkw
Normal file
28
src/wave/gtkw/mux.gtkw
Normal file
@ -0,0 +1,28 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Tue May 19 00:54:32 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/mux.vcd"
|
||||||
|
[dumpfile_mtime] "Tue May 19 00:46:45 2015"
|
||||||
|
[dumpfile_size] 498
|
||||||
|
[savefile] "/home/collin/hack/src/wave/mux.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-19.992342 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 78
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800201
|
||||||
|
-in
|
||||||
|
@29
|
||||||
|
a
|
||||||
|
b
|
||||||
|
sel
|
||||||
|
@1000201
|
||||||
|
-in
|
||||||
|
@28
|
||||||
|
cout
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
29
src/wave/gtkw/mux16.gtkw
Normal file
29
src/wave/gtkw/mux16.gtkw
Normal file
@ -0,0 +1,29 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Tue May 19 00:54:41 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/mux16.vcd"
|
||||||
|
[dumpfile_mtime] "Tue May 19 00:46:45 2015"
|
||||||
|
[dumpfile_size] 1082
|
||||||
|
[savefile] "/home/collin/hack/src/wave/mux16.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-20.022757 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 110
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@22
|
||||||
|
a[15:0]
|
||||||
|
b[15:0]
|
||||||
|
@28
|
||||||
|
sel
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@23
|
||||||
|
cout[15:0]
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
31
src/wave/gtkw/mux4way16.gtkw
Normal file
31
src/wave/gtkw/mux4way16.gtkw
Normal file
@ -0,0 +1,31 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Wed May 20 08:56:25 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/mux4way16.vcd"
|
||||||
|
[dumpfile_mtime] "Wed May 20 06:54:27 2015"
|
||||||
|
[dumpfile_size] 2591
|
||||||
|
[savefile] "/home/collin/hack/src/wave/mux4way16.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-20.066639 1837000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 155
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@22
|
||||||
|
a[15:0]
|
||||||
|
b[15:0]
|
||||||
|
c[15:0]
|
||||||
|
d[15:0]
|
||||||
|
@28
|
||||||
|
sel[1:0]
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@22
|
||||||
|
cout[15:0]
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
35
src/wave/gtkw/mux8way16.gtkw
Normal file
35
src/wave/gtkw/mux8way16.gtkw
Normal file
@ -0,0 +1,35 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Wed May 20 07:06:13 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/mux8way16.vcd"
|
||||||
|
[dumpfile_mtime] "Wed May 20 07:05:19 2015"
|
||||||
|
[dumpfile_size] 8562
|
||||||
|
[savefile] "/home/collin/hack/src/wave/mux8way16.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-21.022757 850000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 161
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@800201
|
||||||
|
-in
|
||||||
|
@23
|
||||||
|
a[15:0]
|
||||||
|
b[15:0]
|
||||||
|
c[15:0]
|
||||||
|
d[15:0]
|
||||||
|
e[15:0]
|
||||||
|
f[15:0]
|
||||||
|
g[15:0]
|
||||||
|
h[15:0]
|
||||||
|
@29
|
||||||
|
sel[2:0]
|
||||||
|
@1000201
|
||||||
|
-in
|
||||||
|
@22
|
||||||
|
cout[15:0]
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
38
src/wave/gtkw/pc.gtkw
Normal file
38
src/wave/gtkw/pc.gtkw
Normal file
@ -0,0 +1,38 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Thu May 21 03:38:54 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/pc.vcd"
|
||||||
|
[dumpfile_mtime] "Thu May 21 03:35:34 2015"
|
||||||
|
[dumpfile_size] 23924
|
||||||
|
[savefile] "/home/collin/hack/src/wave/pc.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-21.976503 27000000 4000000 5000000 6000000 9000000 10000000 11000000 12000000 22000000 28000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[treeopen] pc_0.
|
||||||
|
[treeopen] pc_0.reg_0.
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 158
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 351
|
||||||
|
@29
|
||||||
|
clk
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@22
|
||||||
|
d[15:0]
|
||||||
|
@28
|
||||||
|
reset
|
||||||
|
load
|
||||||
|
inc
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@22
|
||||||
|
cout[15:0]
|
||||||
|
@200
|
||||||
|
-reg
|
||||||
|
@22
|
||||||
|
pc_0.reg_0.cout[15:0]
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
88
src/wave/gtkw/ram8.gtkw
Normal file
88
src/wave/gtkw/ram8.gtkw
Normal file
@ -0,0 +1,88 @@
|
|||||||
|
[*]
|
||||||
|
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
|
||||||
|
[*] Thu May 21 00:28:13 2015
|
||||||
|
[*]
|
||||||
|
[dumpfile] "/home/collin/hack/src/wave/ram8.vcd"
|
||||||
|
[dumpfile_mtime] "Wed May 20 08:41:48 2015"
|
||||||
|
[dumpfile_size] 508704
|
||||||
|
[savefile] "/home/collin/hack/src/wave/ram8.gtkw"
|
||||||
|
[timestart] 0
|
||||||
|
[size] 1920 1200
|
||||||
|
[pos] -1 -1
|
||||||
|
*-24.508835 36500000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||||
|
[treeopen] ram8_0.
|
||||||
|
[treeopen] ram8_0.reg(0).
|
||||||
|
[treeopen] ram8_0.reg(1).
|
||||||
|
[treeopen] ram8_0.reg(2).
|
||||||
|
[treeopen] ram8_0.reg(3).
|
||||||
|
[treeopen] ram8_0.reg(4).
|
||||||
|
[treeopen] ram8_0.reg(5).
|
||||||
|
[treeopen] ram8_0.reg(6).
|
||||||
|
[treeopen] ram8_0.reg(7).
|
||||||
|
[sst_width] 250
|
||||||
|
[signals_width] 171
|
||||||
|
[sst_expanded] 1
|
||||||
|
[sst_vpaned_height] 396
|
||||||
|
@28
|
||||||
|
ram8_0.clk
|
||||||
|
@800200
|
||||||
|
-in
|
||||||
|
@22
|
||||||
|
ram8_0.d[15:0]
|
||||||
|
@28
|
||||||
|
ram8_0.load
|
||||||
|
ram8_0.address[2:0]
|
||||||
|
@1000200
|
||||||
|
-in
|
||||||
|
@800201
|
||||||
|
-out
|
||||||
|
@23
|
||||||
|
ram8_0.cout[15:0]
|
||||||
|
@1000201
|
||||||
|
-out
|
||||||
|
@800200
|
||||||
|
-registers
|
||||||
|
@200
|
||||||
|
-reg000
|
||||||
|
@22
|
||||||
|
[color] 2
|
||||||
|
ram8_0.reg(0).dregister_i.cout[15:0]
|
||||||
|
@200
|
||||||
|
-reg001
|
||||||
|
@22
|
||||||
|
[color] 4
|
||||||
|
ram8_0.reg(1).dregister_i.cout[15:0]
|
||||||
|
@200
|
||||||
|
-reg010
|
||||||
|
@22
|
||||||
|
[color] 6
|
||||||
|
ram8_0.reg(2).dregister_i.cout[15:0]
|
||||||
|
@200
|
||||||
|
-reg011
|
||||||
|
@22
|
||||||
|
[color] 1
|
||||||
|
ram8_0.reg(3).dregister_i.cout[15:0]
|
||||||
|
@200
|
||||||
|
-reg 100
|
||||||
|
@22
|
||||||
|
[color] 3
|
||||||
|
ram8_0.reg(4).dregister_i.cout[15:0]
|
||||||
|
@200
|
||||||
|
-reg101
|
||||||
|
@22
|
||||||
|
[color] 5
|
||||||
|
ram8_0.reg(5).dregister_i.cout[15:0]
|
||||||
|
@200
|
||||||
|
-reg110
|
||||||
|
@22
|
||||||
|
[color] 7
|
||||||
|
ram8_0.reg(6).dregister_i.cout[15:0]
|
||||||
|
@200
|
||||||
|
-reg111
|
||||||
|
@22
|
||||||
|
[color] 2
|
||||||
|
ram8_0.reg(7).dregister_i.cout[15:0]
|
||||||
|
@1000200
|
||||||
|
-registers
|
||||||
|
[pattern_trace] 1
|
||||||
|
[pattern_trace] 0
|
2
src/wave/vcd/.gitignore
vendored
Normal file
2
src/wave/vcd/.gitignore
vendored
Normal file
@ -0,0 +1,2 @@
|
|||||||
|
*
|
||||||
|
!.gitignore
|
2
src/work/.gitignore
vendored
Normal file
2
src/work/.gitignore
vendored
Normal file
@ -0,0 +1,2 @@
|
|||||||
|
*
|
||||||
|
!.gitignore
|
Loading…
Reference in New Issue
Block a user